stegnography.hwh

        </PORT>
        <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps_150M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps_150M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_150M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps_150M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_150M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps_150M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="rst_ps_150M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps_150M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M02_ARESETN" SIGIS="rst" SIGNAME="rst_ps_150M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ps_150M" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M02_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M02_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M02_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M02_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARADDR">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RRESP">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="11" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="11" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="11" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="11" NAME="S00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WID"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ps_M_AXI_GP0" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
            <PORTMAP LOGICAL="WID" PHYSICAL="S00_AXI_wid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps_axi_periph_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M00_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M00_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps_axi_periph_M01_AXI" DATAWIDTH="32" NAME="M01_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M01_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M01_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M01_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M01_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M01_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M01_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M01_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M01_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M01_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M01_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M01_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M01_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M01_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M01_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M01_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M01_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M01_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M01_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M01_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M01_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M01_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M01_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M01_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M01_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M01_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M01_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M01_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M01_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M01_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M01_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M01_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M01_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M01_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M01_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M01_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps_axi_periph_M02_AXI" DATAWIDTH="32" NAME="M02_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M02_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M02_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M02_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M02_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M02_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M02_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M02_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M02_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M02_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M02_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M02_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M02_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M02_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M02_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M02_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M02_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M02_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M02_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M02_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M02_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M02_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M02_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M02_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M02_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M02_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M02_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M02_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M02_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M02_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M02_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M02_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M02_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M02_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M02_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M02_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_ps_150M" HWVERSION="5.0" INSTANCE="rst_ps_150M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="stegnography_rst_ps_150M_0"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="150000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="ps_FCLK_RESET0_N">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps" PORT="FCLK_RESET0_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_ps_150M_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S01_ARESETN"/>
            <CONNECTION INSTANCE="pixel" PORT="ap_rst_n"/>
            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S02_ARESETN"/>
            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_ARESETN"/>
            <CONNECTION INSTANCE="axi_interconnect_0" PORT="ARESETN"/>
            <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_ARESETN"/>
            <CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
            <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_ARESETN"/>
            <CONNECTION INSTANCE="ps_axi_periph" PORT="ARESETN"/>
            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S03_ARESETN"/>
            <CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ARESETN"/>
            <CONNECTION INSTANCE="axi_dma_1" PORT="axi_resetn"/>
            <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_ARESETN"/>
            <CONNECTION INSTANCE="axi_interconnect_0" PORT="M01_ARESETN"/>
            <CONNECTION INSTANCE="ps_axi_periph" PORT="M02_ARESETN"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
  </MODULES>

</EDKSYSTEM>