stegnography.hwh

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Jul  1 23:34:58 2021" VIVADOVERSION="2020.2">

  <SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="stegnography" PACKAGE="clg400" SPEEDGRADE="-1"/>

  <EXTERNALPORTS>
    <PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="ps_DDR_CAS_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_CAS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_cke" SIGIS="undef" SIGNAME="ps_DDR_CKE">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_CKE"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_n" SIGIS="clk" SIGNAME="ps_DDR_Clk_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_Clk_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_p" SIGIS="clk" SIGNAME="ps_DDR_Clk">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_Clk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_cs_n" SIGIS="undef" SIGNAME="ps_DDR_CS_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_CS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="ps_DDR_DRSTB">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_DRSTB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_odt" SIGIS="undef" SIGNAME="ps_DDR_ODT">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_ODT"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_ras_n" SIGIS="undef" SIGNAME="ps_DDR_RAS_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_RAS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="DDR_we_n" SIGIS="undef" SIGNAME="ps_DDR_WEB">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_WEB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="2" NAME="DDR_ba" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_BankAddr">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_BankAddr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="14" NAME="DDR_addr" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_Addr">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_Addr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="3" NAME="DDR_dm" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DM">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_DM"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="31" NAME="DDR_dq" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQ">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_DQ"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_n" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQS_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_DQS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_p" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQS">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_DQS"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="MIO"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
      </CONNECTIONS>
    </PORT>
  </EXTERNALPORTS>

  <EXTERNALINTERFACES>
    <BUSINTERFACE BUSNAME="ps_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
      <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
      <PARAMETER NAME="MEMORY_PART"/>
      <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
      <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
      <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
      <PARAMETER NAME="SLOT" VALUE="Single"/>
      <PARAMETER NAME="CUSTOM_PARTS"/>
      <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
      <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
      <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
      <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
      <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_cas_n"/>
        <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_cke"/>
        <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_ck_n"/>
        <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_ck_p"/>
        <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_cs_n"/>
        <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_reset_n"/>
        <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_odt"/>
        <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_ras_n"/>
        <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_we_n"/>
        <PORTMAP LOGICAL="BA" PHYSICAL="DDR_ba"/>
        <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_addr"/>
        <PORTMAP LOGICAL="DM" PHYSICAL="DDR_dm"/>
        <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_dq"/>
        <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_dqs_n"/>
        <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_dqs_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="ps_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="MIO" PHYSICAL="FIXED_IO_mio"/>
        <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="FIXED_IO_ddr_vrn"/>
        <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="FIXED_IO_ddr_vrp"/>
        <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="FIXED_IO_ps_srstb"/>
        <PORTMAP LOGICAL="PS_CLK" PHYSICAL="FIXED_IO_ps_clk"/>
        <PORTMAP LOGICAL="PS_PORB" PHYSICAL="FIXED_IO_ps_porb"/>
      </PORTMAPS>
    </BUSINTERFACE>
  </EXTERNALINTERFACES>

  <MODULES>
    <MODULE COREREVISION="23" FULLNAME="/axi_dma_0" HWVERSION="7.1" INSTANCE="axi_dma_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="MM2S_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when the multichannel feature is enabled or in Direct Register mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>