README.md

# Embedded Security Project Proposal


1. clone the project 

2. load vitis settings.sh file and run make clean && make

3. open the RTL file in vivado and connect the pins as mentioned in the stenganography.pdf (optional: make necessary clock frequency changes)

4. (optional load Vivado settings.sh file) make

5. Use Test bench files to do the debugging and add changes before synthesizing new overlay.

6. Use the given Jupyter notebook to test your iP.