Update README.md

README.md

 # Embedded Security Project Proposal
-Template used **Stanfordpython project proposal template**
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+1. clone the project 
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+2. load vitis settings.sh file and run make clean && make
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+3. open the RTL file in vivado and connect the pins as mentioned in the stenganography.pdf (optional: make necessary clock frequency changes)
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+4. (optional load Vivado settings.sh file) make
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+5. Use Test bench files to do the debugging and add changes before synthesizing new overlay.
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+6. Use the given Jupyter notebook to test your iP.