diff --git a/overlay.bit b/overlay.bit
index 9f4fc77f330e5075afba0bb25816a9207d742590..127574c895a7cb55a8b1e5543c102302b4531e65 100644
Binary files a/overlay.bit and b/overlay.bit differ
diff --git a/overlay.hwh b/overlay.hwh
index bcd75f50de96f48e01183066384499858077dcb4..4629cf69cb3832ec11b2ebd2ad94d1710cc24c37 100644
--- a/overlay.hwh
+++ b/overlay.hwh
@@ -1,39 +1,9 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Jun 4 03:34:28 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Jun 4 11:52:27 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
- <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="MIO"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="ps_DDR_CAS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="DDR_CAS_n"/>
@@ -109,6 +79,36 @@
<CONNECTION INSTANCE="ps" PORT="DDR_DQS"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="MIO"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
+ </CONNECTIONS>
+ </PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
@@ -1912,6 +1912,95 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
<PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS>
@@ -2013,95 +2102,6 @@
<PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
@@ -2424,7 +2424,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106040328" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106041142" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
@@ -4715,7 +4715,7 @@
<PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
<PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="Component_Name" VALUE="overlay_ps_axi_periph_0"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_ps_axi_periph_1"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
</PARAMETERS>
<PORTS>
@@ -5289,7 +5289,7 @@
<PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
<PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
<PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
- <PARAMETER NAME="Component_Name" VALUE="overlay_rst_ps_50M_0"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_rst_ps_50M_1"/>
<PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
<PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>