diff --git a/overlay.bit b/overlay.bit
index 038b7c47227a97cc0ecd8c3da0fb0db02a7623ba..8bf511f05745c61585260d7ca7e7b400f4eb5a5a 100644
Binary files a/overlay.bit and b/overlay.bit differ
diff --git a/overlay.hwh b/overlay.hwh
index 65f90f4ffc55795777dbdff09e201e34b9d98408..5139bde9fda025f57bed96507301d838cd8e54f0 100644
--- a/overlay.hwh
+++ b/overlay.hwh
@@ -1,39 +1,9 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Jun 22 13:47:55 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Jun 23 13:06:22 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
- <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="MIO"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="ps_DDR_CAS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="DDR_CAS_n"/>
@@ -109,6 +79,36 @@
<CONNECTION INSTANCE="ps" PORT="DDR_DQS"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="MIO"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
+ </CONNECTIONS>
+ </PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
@@ -1912,381 +1912,381 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
+ <PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
+ <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
+ <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
+ <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
+ <PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
+ <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
+ <PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
+ <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
+ <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
+ <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
+ <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
+ <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
+ <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
+ <PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
+ <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
+ <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
+ <PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
+ <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
+ <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
+ <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
+ <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
+ <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
+ <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
+ <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
+ <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
+ <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wid">
@@ -2424,14 +2424,44 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106221334" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106231301" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
<REGISTERS>
+ <REGISTER NAME="key">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of key"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+ <FIELDS>
+ <FIELD NAME="key">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 7 to 0 of key"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ <FIELD NAME="RESERVED">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Reserved. 0s on read."/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="24"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
<REGISTER NAME="selector">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of selector"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2451,7 +2481,7 @@
</REGISTER>
<REGISTER NAME="position1">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of position1"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="32"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2471,7 +2501,7 @@
</REGISTER>
<REGISTER NAME="position2">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of position2"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="32"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="40"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2491,7 +2521,7 @@
</REGISTER>
<REGISTER NAME="stream_count">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of stream_count"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="40"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="48"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2511,7 +2541,7 @@
</REGISTER>
<REGISTER NAME="ascii_i">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ascii_i"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="48"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="56"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2531,7 +2561,7 @@
</REGISTER>
<REGISTER NAME="ascii_o">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ascii_o"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="56"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="64"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2551,7 +2581,7 @@
</REGISTER>
<REGISTER NAME="ascii_o_ctrl">
<PROPERTY NAME="DESCRIPTION" VALUE="Control signal of ascii_o"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="60"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="68"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2583,7 +2613,7 @@
</ADDRESSBLOCK>
</ADDRESSBLOCKS>
<PARAMETERS>
- <PARAMETER NAME="C_S_AXI_CONTROL_ADDR_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_CONTROL_ADDR_WIDTH" VALUE="7"/>
<PARAMETER NAME="C_S_AXI_CONTROL_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="Component_Name" VALUE="overlay_pixel_0"/>
<PARAMETER NAME="clk_period" VALUE="10"/>
@@ -2596,7 +2626,7 @@
<PARAMETER NAME="C_S_AXI_CONTROL_HIGHADDR" VALUE="0x4000FFFF"/>
</PARAMETERS>
<PORTS>
- <PORT DIR="I" LEFT="5" NAME="s_axi_control_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
+ <PORT DIR="I" LEFT="6" NAME="s_axi_control_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_awaddr"/>
</CONNECTIONS>
@@ -2646,7 +2676,7 @@
<CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="5" NAME="s_axi_control_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
+ <PORT DIR="I" LEFT="6" NAME="s_axi_control_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_araddr"/>
</CONNECTIONS>
@@ -2746,7 +2776,7 @@
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps_axi_periph_M01_AXI" DATAWIDTH="32" NAME="s_axi_control" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
- <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
@@ -4889,105 +4919,6 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
@@ -5091,6 +5022,105 @@
<CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>