diff --git a/rtl-proj/rtl.gen/sources_1/bd/overlay/hw_handoff/overlay.hwh b/rtl-proj/rtl.gen/sources_1/bd/overlay/hw_handoff/overlay.hwh
index 18b44453cef2d954fdaf306eb05ed79e431a8872..2524086197edf0e05ef4864f8c750e4232b7a1c6 100644
--- a/rtl-proj/rtl.gen/sources_1/bd/overlay/hw_handoff/overlay.hwh
+++ b/rtl-proj/rtl.gen/sources_1/bd/overlay/hw_handoff/overlay.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Jun 3 00:41:47 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Jun 4 01:47:09 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
@@ -159,7 +159,7 @@
</EXTERNALINTERFACES>
<MODULES>
- <MODULE COREREVISION="23" FULLNAME="/axi_dma_1" HWVERSION="7.1" INSTANCE="axi_dma_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
+ <MODULE COREREVISION="23" FULLNAME="/axi_dma_0" HWVERSION="7.1" INSTANCE="axi_dma_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
<DOCUMENTS>
<DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
</DOCUMENTS>
@@ -1012,7 +1012,7 @@
<PARAMETER NAME="C_INCLUDE_S2MM_DRE" VALUE="0"/>
<PARAMETER NAME="C_INCREASE_THROUGHPUT" VALUE="0"/>
<PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
- <PARAMETER NAME="Component_Name" VALUE="overlay_axi_dma_1_0"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_axi_dma_0_0"/>
<PARAMETER NAME="c_include_sg" VALUE="0"/>
<PARAMETER NAME="c_enable_multi_channel" VALUE="0"/>
<PARAMETER NAME="c_num_mm2s_channels" VALUE="1"/>
@@ -1063,279 +1063,279 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awvalid">
+ <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awready">
+ <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awaddr">
+ <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wvalid">
+ <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wready">
+ <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wdata">
+ <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bresp">
+ <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bvalid">
+ <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bready">
+ <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_arvalid">
+ <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_arready">
+ <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_araddr">
+ <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rvalid">
+ <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rready">
+ <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rdata">
+ <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rresp">
+ <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_araddr">
+ <PORT DIR="O" LEFT="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arlen">
+ <PORT DIR="O" LEFT="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arlen"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arsize">
+ <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arsize"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arburst">
+ <PORT DIR="O" LEFT="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arburst"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arprot">
+ <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arprot"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arcache">
+ <PORT DIR="O" LEFT="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arcache"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="m_axi_mm2s_arvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arvalid">
+ <PORT DIR="O" NAME="m_axi_mm2s_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="m_axi_mm2s_arready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arready">
+ <PORT DIR="I" NAME="m_axi_mm2s_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rdata">
+ <PORT DIR="I" LEFT="31" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rresp">
+ <PORT DIR="I" LEFT="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="m_axi_mm2s_rlast" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rlast">
+ <PORT DIR="I" NAME="m_axi_mm2s_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="m_axi_mm2s_rvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rvalid">
+ <PORT DIR="I" NAME="m_axi_mm2s_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="m_axi_mm2s_rready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rready">
+ <PORT DIR="O" NAME="m_axi_mm2s_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="mm2s_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
- <PORT DIR="O" LEFT="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tdata">
+ <PORT DIR="O" LEFT="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="din_TDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tkeep">
+ <PORT DIR="O" LEFT="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tkeep">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="din_TKEEP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="m_axis_mm2s_tvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tvalid">
+ <PORT DIR="O" NAME="m_axis_mm2s_tvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="din_TVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="m_axis_mm2s_tready" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tready">
+ <PORT DIR="I" NAME="m_axis_mm2s_tready" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="din_TREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="m_axis_mm2s_tlast" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tlast">
+ <PORT DIR="O" NAME="m_axis_mm2s_tlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tlast">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="din_TLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awaddr">
+ <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awlen">
+ <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awlen"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awsize">
+ <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awsize"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awburst">
+ <PORT DIR="O" LEFT="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awburst"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awprot">
+ <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awprot"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awcache">
+ <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awcache"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awvalid">
+ <PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="m_axi_s2mm_awready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awready">
+ <PORT DIR="I" NAME="m_axi_s2mm_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wdata">
+ <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wstrb">
+ <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="m_axi_s2mm_wlast" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wlast">
+ <PORT DIR="O" NAME="m_axi_s2mm_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="m_axi_s2mm_wvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wvalid">
+ <PORT DIR="O" NAME="m_axi_s2mm_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="m_axi_s2mm_wready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wready">
+ <PORT DIR="I" NAME="m_axi_s2mm_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_bresp">
+ <PORT DIR="I" LEFT="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="m_axi_s2mm_bvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_bvalid">
+ <PORT DIR="I" NAME="m_axi_s2mm_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="m_axi_s2mm_bready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_bready">
+ <PORT DIR="O" NAME="m_axi_s2mm_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="s2mm_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
- <PORT DIR="I" LEFT="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tdata">
+ <PORT DIR="I" LEFT="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tdata">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="dout_TDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tkeep">
+ <PORT DIR="I" LEFT="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tkeep">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="dout_TKEEP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="s_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tvalid">
+ <PORT DIR="I" NAME="s_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="dout_TVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="s_axis_s2mm_tready" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tready">
+ <PORT DIR="O" NAME="s_axis_s2mm_tready" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tready">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="dout_TREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="s_axis_s2mm_tlast" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tlast">
+ <PORT DIR="I" NAME="s_axis_s2mm_tlast" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tlast">
<CONNECTIONS>
<CONNECTION INSTANCE="pixel" PORT="dout_TLAST"/>
</CONNECTIONS>
@@ -1366,13 +1366,13 @@
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
- <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
- <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
<PARAMETER NAME="PHASE" VALUE="0.000"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
- <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
- <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
@@ -1395,7 +1395,7 @@
<PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_lite_wvalid"/>
</PORTMAPS>
</BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_dma_1_M_AXI_MM2S" DATAWIDTH="32" NAME="M_AXI_MM2S" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_MM2S" DATAWIDTH="32" NAME="M_AXI_MM2S" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
@@ -1443,7 +1443,7 @@
<PORTMAP LOGICAL="RVALID" PHYSICAL="m_axi_mm2s_rvalid"/>
</PORTMAPS>
</BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_dma_1_M_AXI_S2MM" DATAWIDTH="32" NAME="M_AXI_S2MM" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_S2MM" DATAWIDTH="32" NAME="M_AXI_S2MM" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
@@ -1494,7 +1494,7 @@
<PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_s2mm_wvalid"/>
</PORTMAPS>
</BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_dma_1_M_AXIS_MM2S" NAME="M_AXIS_MM2S" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXIS_MM2S" NAME="M_AXIS_MM2S" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
<PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
<PARAMETER NAME="TID_WIDTH" VALUE="0"/>
@@ -1912,383 +1912,383 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
+ <PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
+ <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
+ <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
+ <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
+ <PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
+ <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
+ <PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
+ <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
+ <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
+ <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
+ <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
+ <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
+ <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
+ <PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
+ <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
+ <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
+ <PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_araddr">
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_araddr"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arlen">
+ <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_arlen"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arsize">
+ <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_arsize"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arburst">
+ <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_arburst"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arcache">
+ <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_arcache"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arprot">
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_arprot"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arvalid">
+ <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_arvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_arready">
+ <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_arready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rdata">
+ <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_rdata"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rresp">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_rresp"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rlast">
+ <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_rlast"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rvalid">
+ <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_rvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_mm2s_rready">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_rready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awaddr">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_awaddr"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awlen">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_awlen"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awsize">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_awsize"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awburst">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_awburst"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awcache">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_awcache"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awprot">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_awprot"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awvalid">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_awvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awready">
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_awready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wdata">
+ <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_wdata"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wstrb">
+ <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_wstrb"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wlast">
+ <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_wlast"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wvalid">
+ <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_wvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_wready">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_wready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_bresp">
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_bresp"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_bvalid">
+ <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_bvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_bready">
+ <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_bready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WID"/>
@@ -2296,7 +2296,7 @@
</PORT>
</PORTS>
<BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi_dma_1_M_AXI_MM2S" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_MM2S" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
@@ -2381,7 +2381,7 @@
<PORTMAP LOGICAL="WID" PHYSICAL="M00_AXI_wid"/>
</PORTMAPS>
</BUSINTERFACE>
- <BUSINTERFACE BUSNAME="axi_dma_1_M_AXI_S2MM" DATAWIDTH="32" NAME="S01_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_S2MM" DATAWIDTH="32" NAME="S01_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
<PORTMAP LOGICAL="AWID" PHYSICAL="S01_AXI_awid"/>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="S01_AXI_awaddr"/>
@@ -2424,18 +2424,203 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106030024" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106040136" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
- <PARAMETERS>
- <PARAMETER NAME="Component_Name" VALUE="overlay_pixel_0"/>
- <PARAMETER NAME="clk_period" VALUE="10"/>
- <PARAMETER NAME="machine" VALUE="64"/>
- <PARAMETER NAME="combinational" VALUE="0"/>
- <PARAMETER NAME="latency" VALUE="1"/>
+ <ADDRESSBLOCKS>
+ <ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
+ <REGISTERS>
+ <REGISTER NAME="w">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of w"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+ <FIELDS>
+ <FIELD NAME="w">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of w"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="len_i">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of len_i"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+ <FIELDS>
+ <FIELD NAME="len_i">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of len_i"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="len_o">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of len_o"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="32"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+ <FIELDS>
+ <FIELD NAME="len_o">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of len_o"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="len_o_ctrl">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Control signal of len_o"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="36"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+ <FIELDS>
+ <FIELD NAME="len_o_ap_vld">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Control signal len_o_ap_vld"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="RESERVED">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Reserved. 0s on read."/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="31"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ </REGISTERS>
+ </ADDRESSBLOCK>
+ </ADDRESSBLOCKS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_S_AXI_CONTROL_ADDR_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_CONTROL_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_pixel_0"/>
+ <PARAMETER NAME="clk_period" VALUE="10"/>
+ <PARAMETER NAME="machine" VALUE="64"/>
+ <PARAMETER NAME="combinational" VALUE="0"/>
+ <PARAMETER NAME="latency" VALUE="1"/>
<PARAMETER NAME="II" VALUE="x"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ <PARAMETER NAME="C_S_AXI_CONTROL_BASEADDR" VALUE="0x40000000"/>
+ <PARAMETER NAME="C_S_AXI_CONTROL_HIGHADDR" VALUE="0x4000FFFF"/>
</PARAMETERS>
<PORTS>
+ <PORT DIR="I" LEFT="5" NAME="s_axi_control_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_control_AWVALID" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_control_AWREADY" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="s_axi_control_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="s_axi_control_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_control_WVALID" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_control_WREADY" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_control_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_control_BVALID" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_control_BREADY" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="5" NAME="s_axi_control_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_control_ARVALID" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_control_ARREADY" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="s_axi_control_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_control_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_control_RVALID" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_control_RREADY" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
<PORT CLKFREQUENCY="50000000" DIR="I" NAME="ap_clk" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
@@ -2446,61 +2631,113 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="din_TVALID" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tvalid">
+ <PORT DIR="I" NAME="din_TVALID" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axis_mm2s_tvalid"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="din_TREADY" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tready">
+ <PORT DIR="O" NAME="din_TREADY" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axis_mm2s_tready"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="din_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tdata">
+ <PORT DIR="I" LEFT="31" NAME="din_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axis_mm2s_tdata"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="din_TLAST" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tlast">
+ <PORT DIR="I" LEFT="0" NAME="din_TLAST" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axis_mm2s_tlast"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="din_TKEEP" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axis_mm2s_tkeep">
+ <PORT DIR="I" LEFT="3" NAME="din_TKEEP" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tkeep">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axis_mm2s_tkeep"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tkeep"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="din_TSTRB" RIGHT="0" SIGIS="undef"/>
- <PORT DIR="O" NAME="dout_TVALID" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tvalid">
+ <PORT DIR="O" NAME="dout_TVALID" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axis_s2mm_tvalid"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="dout_TREADY" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tready">
+ <PORT DIR="I" NAME="dout_TREADY" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axis_s2mm_tready"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="dout_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tdata">
+ <PORT DIR="O" LEFT="31" NAME="dout_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axis_s2mm_tdata"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="dout_TLAST" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tlast">
+ <PORT DIR="O" LEFT="0" NAME="dout_TLAST" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axis_s2mm_tlast"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="dout_TKEEP" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axis_s2mm_tkeep">
+ <PORT DIR="O" LEFT="3" NAME="dout_TKEEP" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tkeep">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axis_s2mm_tkeep"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tkeep"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="dout_TSTRB" RIGHT="0" SIGIS="undef"/>
</PORTS>
<BUSINTERFACES>
- <BUSINTERFACE BUSNAME="axi_dma_1_M_AXIS_MM2S" NAME="din" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
+ <BUSINTERFACE BUSNAME="ps_axi_periph_M01_AXI" DATAWIDTH="32" NAME="s_axi_control" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_control_AWADDR"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_control_AWVALID"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_control_AWREADY"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_control_WDATA"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_control_WSTRB"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_control_WVALID"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_control_WREADY"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_control_BRESP"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_control_BVALID"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_control_BREADY"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_control_ARADDR"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_control_ARVALID"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_control_ARREADY"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_control_RDATA"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_control_RRESP"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_control_RVALID"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_control_RREADY"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXIS_MM2S" NAME="din" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
<PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
<PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
@@ -3893,16 +4130,17 @@
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ACLK"/>
<CONNECTION INSTANCE="ps_axi_periph" PORT="S00_ACLK"/>
<CONNECTION INSTANCE="rst_ps_50M" PORT="slowest_sync_clk"/>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_aclk"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_aclk"/>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_ACLK"/>
<CONNECTION INSTANCE="ps_axi_periph" PORT="ACLK"/>
<CONNECTION INSTANCE="pixel" PORT="ap_clk"/>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_mm2s_aclk"/>
- <CONNECTION INSTANCE="axi_dma_1" PORT="m_axi_s2mm_aclk"/>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_ACLK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_aclk"/>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ACLK"/>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ACLK"/>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ACLK"/>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="ACLK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ACLK"/>
</CONNECTIONS>
</PORT>
@@ -4220,10 +4458,12 @@
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
- <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41E00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41E0FFFF" INSTANCE="axi_dma_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
+ <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_S_AXI_CONTROL_BASEADDR" BASEVALUE="0x40000000" HIGHNAME="C_S_AXI_CONTROL_HIGHADDR" HIGHVALUE="0x4000FFFF" INSTANCE="pixel" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi_control"/>
+ <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41E00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41E0FFFF" INSTANCE="axi_dma_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
</MEMORYMAP>
<PERIPHERALS>
- <PERIPHERAL INSTANCE="axi_dma_1"/>
+ <PERIPHERAL INSTANCE="pixel"/>
+ <PERIPHERAL INSTANCE="axi_dma_0"/>
</PERIPHERALS>
</MODULE>
<MODULE COREREVISION="23" FULLNAME="/ps_axi_periph" HWVERSION="2.1" INSTANCE="ps_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
@@ -4232,7 +4472,7 @@
</DOCUMENTS>
<PARAMETERS>
<PARAMETER NAME="NUM_SI" VALUE="1"/>
- <PARAMETER NAME="NUM_MI" VALUE="1"/>
+ <PARAMETER NAME="NUM_MI" VALUE="2"/>
<PARAMETER NAME="STRATEGY" VALUE="0"/>
<PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
<PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
@@ -4579,84 +4819,104 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_araddr">
+ <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_araddr"/>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_arready">
+ <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_arready"/>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_arvalid">
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_arvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awaddr">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_awaddr"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awready">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_awready"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_awvalid">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_awvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bready">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_bready"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bresp">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_bresp"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_bvalid">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_bvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rdata">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rdata"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rready">
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rready"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rresp">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rresp"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WSTRB"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_rvalid">
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wdata">
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_wdata"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wready">
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_wready"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_1_s_axi_lite_wvalid">
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_wvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARADDR">
@@ -4664,54 +4924,54 @@
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BRESP"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARQOS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RDATA"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RDATA"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RRESP">
@@ -4719,198 +4979,368 @@
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RRESP"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RLAST"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RVALID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WDATA"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
+ <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARBURST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARCACHE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">
+ <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLEN"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLOCK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARPROT"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARQOS"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARSIZE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
+ <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWBURST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWCACHE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="11" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWID">
+ <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLEN"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLOCK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWPROT"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWQOS"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
+ <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWSIZE"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="11" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BID">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BID"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="11" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RID">
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RID"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
+ <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RLAST"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="11" NAME="S00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WID">
+ <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WID"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WLAST"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WSTRB"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WID"/>
</CONNECTIONS>
</PORT>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps_M_AXI_GP0" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
- <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
- <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
- <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
- <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
- <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
- <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
- <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
- <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
- <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
- <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
- <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
- <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
- <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
- <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
- <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
- <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
- <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
- <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
<PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
- <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
- <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
- <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
- <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
- <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
<PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
<PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
- <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
<PORTMAP LOGICAL="WID" PHYSICAL="S00_AXI_wid"/>
- <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
- <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="ps_axi_periph_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PORTMAPS>
- <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
- <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
- <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
- <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWREGION" PHYSICAL="M00_AXI_awregion"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
- <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARREGION" PHYSICAL="M00_AXI_arregion"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
- <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
- <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
- <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
- <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="ps_axi_periph_M01_AXI" DATAWIDTH="32" NAME="M01_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="M01_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="M01_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M01_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="M01_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M01_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M01_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="M01_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWREGION" PHYSICAL="M01_AXI_awregion"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="M01_AXI_awqos"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="M01_AXI_awvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M01_AXI_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M01_AXI_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="M01_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="M01_AXI_wlast"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M01_AXI_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M01_AXI_wready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="M01_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="M01_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M01_AXI_bready"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M01_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="M01_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M01_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="M01_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M01_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M01_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="M01_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARREGION" PHYSICAL="M01_AXI_arregion"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="M01_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M01_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M01_AXI_arready"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="M01_AXI_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="M01_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="M01_AXI_rlast"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="M01_AXI_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M01_AXI_rready"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
@@ -4955,10 +5385,11 @@
<PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="S00_ARESETN"/>
- <CONNECTION INSTANCE="axi_dma_1" PORT="axi_resetn"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M00_ARESETN"/>
<CONNECTION INSTANCE="ps_axi_periph" PORT="ARESETN"/>
<CONNECTION INSTANCE="pixel" PORT="ap_rst_n"/>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M01_ARESETN"/>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ARESETN"/>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ARESETN"/>
<CONNECTION INSTANCE="axi_mem_intercon" PORT="ARESETN"/>
diff --git a/rtl-proj/rtl.runs/impl_1/.Vivado_Implementation.queue.rst b/rtl-proj/rtl.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/rtl-proj/rtl.runs/impl_1/.init_design.begin.rst b/rtl-proj/rtl.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e698586185fd05c583988cc6e0d5d9b33a2020f1
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mh02127" Host="" Pid="1655663">
+ </Process>
+</ProcessHandle>
diff --git a/rtl-proj/rtl.runs/impl_1/.init_design.end.rst b/rtl-proj/rtl.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/rtl-proj/rtl.runs/impl_1/.opt_design.begin.rst b/rtl-proj/rtl.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e698586185fd05c583988cc6e0d5d9b33a2020f1
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mh02127" Host="" Pid="1655663">
+ </Process>
+</ProcessHandle>
diff --git a/rtl-proj/rtl.runs/impl_1/.opt_design.end.rst b/rtl-proj/rtl.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/rtl-proj/rtl.runs/impl_1/.phys_opt_design.begin.rst b/rtl-proj/rtl.runs/impl_1/.phys_opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e698586185fd05c583988cc6e0d5d9b33a2020f1
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/.phys_opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mh02127" Host="" Pid="1655663">
+ </Process>
+</ProcessHandle>
diff --git a/rtl-proj/rtl.runs/impl_1/.phys_opt_design.end.rst b/rtl-proj/rtl.runs/impl_1/.phys_opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/rtl-proj/rtl.runs/impl_1/.place_design.begin.rst b/rtl-proj/rtl.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e698586185fd05c583988cc6e0d5d9b33a2020f1
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mh02127" Host="" Pid="1655663">
+ </Process>
+</ProcessHandle>
diff --git a/rtl-proj/rtl.runs/impl_1/.place_design.end.rst b/rtl-proj/rtl.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/rtl-proj/rtl.runs/impl_1/.route_design.begin.rst b/rtl-proj/rtl.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e698586185fd05c583988cc6e0d5d9b33a2020f1
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mh02127" Host="" Pid="1655663">
+ </Process>
+</ProcessHandle>
diff --git a/rtl-proj/rtl.runs/impl_1/.route_design.end.rst b/rtl-proj/rtl.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/rtl-proj/rtl.runs/impl_1/.vivado.begin.rst b/rtl-proj/rtl.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..00d61b94741d00d34f4306ffe8e1de9514e8daab
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="mh02127" Host="joan" Pid="1655621" HostCore="24" HostMemory="231076096">
+ </Process>
+</ProcessHandle>
diff --git a/rtl-proj/rtl.runs/impl_1/.vivado.end.rst b/rtl-proj/rtl.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/rtl-proj/rtl.runs/impl_1/.write_bitstream.begin.rst b/rtl-proj/rtl.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e698586185fd05c583988cc6e0d5d9b33a2020f1
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mh02127" Host="" Pid="1655663">
+ </Process>
+</ProcessHandle>
diff --git a/rtl-proj/rtl.runs/impl_1/.write_bitstream.end.rst b/rtl-proj/rtl.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/rtl-proj/rtl.runs/impl_1/ISEWrap.js b/rtl-proj/rtl.runs/impl_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..3e83de1127090c7eb60bee1be4a6e016516127b6
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/rtl-proj/rtl.runs/impl_1/ISEWrap.sh b/rtl-proj/rtl.runs/impl_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..f679f2e86873e3482adf4a51d722e917f3d4aab2
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,67 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/rtl-proj/rtl.runs/impl_1/gen_run.xml b/rtl-proj/rtl.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..c939e6341fd2646fe9c6b95d6b1d9db494439e08
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/gen_run.xml
@@ -0,0 +1,126 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7z020clg400-1" LaunchTime="1622764034">
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="BITSTR-SYSDEF" Name="overlay.sysdef"/>
+ <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+ <File Type="BITSTR-LTX" Name="overlay.ltx"/>
+ <File Type="BG-BGN" Name="overlay.bgn"/>
+ <File Type="NPI_FILE" Name="overlay.npi"/>
+ <File Type="BG-DRC" Name="overlay.drc"/>
+ <File Type="RNPI_FILE" Name="overlay.rnpi"/>
+ <File Type="CFI_FILE" Name="overlay.cfi"/>
+ <File Type="RCFI_FILE" Name="overlay.rcfi"/>
+ <File Type="PDI-FILE" Name="overlay.pdi"/>
+ <File Type="BITSTR-MMI" Name="overlay.mmi"/>
+ <File Type="BITSTR-BMM" Name="overlay_bd.bmm"/>
+ <File Type="BITSTR-NKY" Name="overlay.nky"/>
+ <File Type="BITSTR-RBT" Name="overlay.rbt"/>
+ <File Type="BITSTR-MSK" Name="overlay.msk"/>
+ <File Type="RBD_FILE" Name="overlay.rbd"/>
+ <File Type="BG-BIN" Name="overlay.bin"/>
+ <File Type="BG-BIT" Name="overlay.bit"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="overlay_bus_skew_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="overlay_bus_skew_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="overlay_bus_skew_postroute_physopted.rpt"/>
+ <File Type="RDI-RDI" Name="overlay.vdi"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="overlay_timing_summary_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="overlay_timing_summary_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING" Name="overlay_timing_summary_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="overlay_postroute_physopt_bb.dcp"/>
+ <File Type="POSTROUTE-PHYSOPT-DCP" Name="overlay_postroute_physopt.dcp"/>
+ <File Type="ROUTE-BUS-SKEW" Name="overlay_bus_skew_routed.rpt"/>
+ <File Type="ROUTE-CLK" Name="overlay_clock_utilization_routed.rpt"/>
+ <File Type="ROUTE-SIMILARITY" Name="overlay_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-TIMING-RPX" Name="overlay_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-TIMING-PB" Name="overlay_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="overlay_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="overlay_route_status.pb"/>
+ <File Type="ROUTE-STATUS" Name="overlay_route_status.rpt"/>
+ <File Type="ROUTE-PWR-RPX" Name="overlay_power_routed.rpx"/>
+ <File Type="ROUTE-PWR-SUM" Name="overlay_power_summary_routed.pb"/>
+ <File Type="ROUTE-PWR" Name="overlay_power_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="overlay_methodology_drc_routed.pb"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="overlay_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="overlay_methodology_drc_routed.rpt"/>
+ <File Type="ROUTE-DRC-RPX" Name="overlay_drc_routed.rpx"/>
+ <File Type="ROUTE-DRC-PB" Name="overlay_drc_routed.pb"/>
+ <File Type="ROUTE-DRC" Name="overlay_drc_routed.rpt"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="overlay_routed_bb.dcp"/>
+ <File Type="ROUTE-DCP" Name="overlay_routed.dcp"/>
+ <File Type="ROUTE-ERROR-DCP" Name="overlay_routed_error.dcp"/>
+ <File Type="PHYSOPT-TIMING" Name="overlay_timing_summary_physopted.rpt"/>
+ <File Type="PHYSOPT-DRC" Name="overlay_drc_physopted.rpt"/>
+ <File Type="PHYSOPT-DCP" Name="overlay_physopt.dcp"/>
+ <File Type="POSTPLACE-PWROPT-TIMING" Name="overlay_timing_summary_postplace_pwropted.rpt"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="overlay_postplace_pwropt.dcp"/>
+ <File Type="PLACE-TIMING" Name="overlay_timing_summary_placed.rpt"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="overlay_incremental_reuse_pre_placed.rpt"/>
+ <File Type="PLACE-SIMILARITY" Name="overlay_incremental_reuse_placed.rpt"/>
+ <File Type="PLACE-CTRL" Name="overlay_control_sets_placed.rpt"/>
+ <File Type="PLACE-UTIL-PB" Name="overlay_utilization_placed.pb"/>
+ <File Type="PLACE-UTIL" Name="overlay_utilization_placed.rpt"/>
+ <File Type="PLACE-CLK" Name="overlay_clock_utilization_placed.rpt"/>
+ <File Type="PLACE-IO" Name="overlay_io_placed.rpt"/>
+ <File Type="PLACE-DCP" Name="overlay_placed.dcp"/>
+ <File Type="PWROPT-TIMING" Name="overlay_timing_summary_pwropted.rpt"/>
+ <File Type="PWROPT-DRC" Name="overlay_drc_pwropted.rpt"/>
+ <File Type="PWROPT-DCP" Name="overlay_pwropt.dcp"/>
+ <File Type="OPT-TIMING" Name="overlay_timing_summary_opted.rpt"/>
+ <File Type="OPT-HWDEF" Name="overlay.hwdef"/>
+ <File Type="OPT-METHODOLOGY-DRC" Name="overlay_methodology_drc_opted.rpt"/>
+ <File Type="OPT-DRC" Name="overlay_drc_opted.rpt"/>
+ <File Type="OPT-DCP" Name="overlay_opt.dcp"/>
+ <File Type="INIT-TIMING" Name="overlay_timing_summary_init.rpt"/>
+ <File Type="ROUTE-BUS-SKEW-RPX" Name="overlay_bus_skew_routed.rpx"/>
+ <File Type="REPORTS-TCL" Name="overlay_reports.tcl"/>
+ <File Type="ROUTE-BUS-SKEW-PB" Name="overlay_bus_skew_routed.pb"/>
+ <File Type="PA-TCL" Name="overlay.tcl"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/bd/overlay/overlay.bd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="overlay"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_auto_pc_0"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_auto_pc_1"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_auto_us_1"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_xbar_1"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_xbar_0"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_auto_us_0"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_rst_ps_50M_0"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_ps_0"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_pixel_0"/>
+ <BlockFileSet Type="BlockSrcs" Name="overlay_axi_dma_0_0"/>
+</GenRun>
diff --git a/rtl-proj/rtl.runs/impl_1/htr.txt b/rtl-proj/rtl.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..3cdb784614b91e886a168b15dc79df3de5aedf4e
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/htr.txt
@@ -0,0 +1,9 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+#
+
+vivado -log overlay.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source overlay.tcl -notrace
diff --git a/rtl-proj/rtl.runs/impl_1/init_design.pb b/rtl-proj/rtl.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..a2bf1e52b95207679ce1da522866907dcb054b4b
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/init_design.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/opt_design.pb b/rtl-proj/rtl.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..8038570aa9ef126382832b9f050c40972014006f
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/opt_design.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay.bit b/rtl-proj/rtl.runs/impl_1/overlay.bit
index 4db9a42c46cb96adaeb3aa4106feccd303bad314..e64904d65bfcf49dca9904d073a791aeeeffef5d 100644
Binary files a/rtl-proj/rtl.runs/impl_1/overlay.bit and b/rtl-proj/rtl.runs/impl_1/overlay.bit differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay.hwdef b/rtl-proj/rtl.runs/impl_1/overlay.hwdef
new file mode 100644
index 0000000000000000000000000000000000000000..204c87ffc4c15026408eb45b5f2846f02eca6070
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay.hwdef differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay.tcl b/rtl-proj/rtl.runs/impl_1/overlay.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..51290c4bde3787b10541a10113c11f74a75a5b39
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay.tcl
@@ -0,0 +1,337 @@
+#
+# Report generation script generated by Vivado
+#
+
+proc create_report { reportName command } {
+ set status "."
+ append status $reportName ".fail"
+ if { [file exists $status] } {
+ eval file delete [glob $status]
+ }
+ send_msg_id runtcl-4 info "Executing : $command"
+ set retval [eval catch { $command } msg]
+ if { $retval != 0 } {
+ set fp [open $status w]
+ close $fp
+ send_msg_id runtcl-5 warning "$msg"
+ }
+}
+namespace eval ::optrace {
+ variable script "/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay.tcl"
+ variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc start_step { step } {
+ set stopFile ".stop.rst"
+ if {[file isfile .stop.rst]} {
+ puts ""
+ puts "*** Halting run - EA reset detected ***"
+ puts ""
+ puts ""
+ return -code error
+ }
+ set beginFile ".$step.begin.rst"
+ set platform "$::tcl_platform(platform)"
+ set user "$::tcl_platform(user)"
+ set pid [pid]
+ set host ""
+ if { [string equal $platform unix] } {
+ if { [info exist ::env(HOSTNAME)] } {
+ set host $::env(HOSTNAME)
+ } elseif { [info exist ::env(HOST)] } {
+ set host $::env(HOST)
+ }
+ } else {
+ if { [info exist ::env(COMPUTERNAME)] } {
+ set host $::env(COMPUTERNAME)
+ }
+ }
+ set ch [open $beginFile w]
+ puts $ch "<?xml version=\"1.0\"?>"
+ puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+ puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+ puts $ch " </Process>"
+ puts $ch "</ProcessHandle>"
+ close $ch
+}
+
+proc end_step { step } {
+ set endFile ".$step.end.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+proc step_failed { step } {
+ set endFile ".$step.error.rst"
+ set ch [open $endFile w]
+ close $ch
+OPTRACE "impl_1" END { }
+}
+
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+ create_msg_db init_design.pb
+ set_param chipscope.maxJobs 1
+OPTRACE "create in-memory project" START { }
+ create_project -in_memory -part xc7z020clg400-1
+ set_property design_mode GateLvl [current_fileset]
+ set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+ set_property webtalk.parent_dir /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.cache/wt [current_project]
+ set_property parent.project_path /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.xpr [current_project]
+ set_property ip_repo_paths /home/mh02127/pixel_manipulation/embedded-security-project/hls-proj [current_project]
+ update_ip_catalog
+ set_property ip_output_repo /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.cache/ip [current_project]
+ set_property ip_cache_permissions {read write} [current_project]
+ set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+ add_files -quiet /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/synth_1/overlay.dcp
+ set_msg_config -source 4 -id {BD 41-1661} -limit 0
+ set_param project.isImplRun true
+ add_files /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.srcs/sources_1/bd/overlay/overlay.bd
+ set_param project.isImplRun false
+OPTRACE "read constraints: implementation" START { }
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+ set_param project.isImplRun true
+ link_design -top overlay -part xc7z020clg400-1
+OPTRACE "link_design" END { }
+ set_param project.isImplRun false
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+ write_hwdef -force -file overlay.hwdef
+OPTRACE "init_design_write_hwdef" END { }
+ close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+ step_failed init_design
+ return -code error $RESULT
+} else {
+ end_step init_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+ create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+ opt_design
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force overlay_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+OPTRACE "opt_design reports" START { REPORT }
+ create_report "impl_1_opt_report_drc_0" "report_drc -file overlay_drc_opted.rpt -pb overlay_drc_opted.pb -rpx overlay_drc_opted.rpx"
+OPTRACE "opt_design reports" END { }
+ close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed opt_design
+ return -code error $RESULT
+} else {
+ end_step opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+ create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+ if { [llength [get_debug_cores -quiet] ] > 0 } {
+OPTRACE "implement_debug_core" START { }
+ implement_debug_core
+OPTRACE "implement_debug_core" END { }
+ }
+OPTRACE "place_design" START { }
+ place_design
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force overlay_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+OPTRACE "place_design reports" START { REPORT }
+ create_report "impl_1_place_report_io_0" "report_io -file overlay_io_placed.rpt"
+ create_report "impl_1_place_report_utilization_0" "report_utilization -file overlay_utilization_placed.rpt -pb overlay_utilization_placed.pb"
+ create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file overlay_control_sets_placed.rpt"
+OPTRACE "place_design reports" END { }
+ close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+ step_failed place_design
+ return -code error $RESULT
+} else {
+ end_step place_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
+start_step phys_opt_design
+set ACTIVE_STEP phys_opt_design
+set rc [catch {
+ create_msg_db phys_opt_design.pb
+OPTRACE "read constraints: phys_opt_design" START { }
+OPTRACE "read constraints: phys_opt_design" END { }
+OPTRACE "phys_opt_design" START { }
+ phys_opt_design
+OPTRACE "phys_opt_design" END { }
+OPTRACE "read constraints: phys_opt_design_post" START { }
+OPTRACE "read constraints: phys_opt_design_post" END { }
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force overlay_physopt.dcp
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
+OPTRACE "phys_opt_design report" START { REPORT }
+OPTRACE "phys_opt_design report" END { }
+ close_msg_db -file phys_opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed phys_opt_design
+ return -code error $RESULT
+} else {
+ end_step phys_opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Physical Opt Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+ create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+ route_design
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force overlay_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design reports" START { REPORT }
+ create_report "impl_1_route_report_drc_0" "report_drc -file overlay_drc_routed.rpt -pb overlay_drc_routed.pb -rpx overlay_drc_routed.rpx"
+ create_report "impl_1_route_report_methodology_0" "report_methodology -file overlay_methodology_drc_routed.rpt -pb overlay_methodology_drc_routed.pb -rpx overlay_methodology_drc_routed.rpx"
+ create_report "impl_1_route_report_power_0" "report_power -file overlay_power_routed.rpt -pb overlay_power_summary_routed.pb -rpx overlay_power_routed.rpx"
+ create_report "impl_1_route_report_route_status_0" "report_route_status -file overlay_route_status.rpt -pb overlay_route_status.pb"
+ create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file overlay_timing_summary_routed.rpt -pb overlay_timing_summary_routed.pb -rpx overlay_timing_summary_routed.rpx -warn_on_violation "
+ create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file overlay_incremental_reuse_routed.rpt"
+ create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file overlay_clock_utilization_routed.rpt"
+ create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file overlay_bus_skew_routed.rpt -pb overlay_bus_skew_routed.pb -rpx overlay_bus_skew_routed.rpx"
+OPTRACE "route_design reports" END { }
+OPTRACE "route_design misc" START { }
+ close_msg_db -file route_design.pb
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+} RESULT]
+if {$rc} {
+ write_checkpoint -force overlay_routed_error.dcp
+ step_failed route_design
+ return -code error $RESULT
+} else {
+ end_step route_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+ create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+ set_property XPM_LIBRARIES {XPM_CDC XPM_FIFO XPM_MEMORY} [current_project]
+ catch { write_mem_info -force -no_partial_mmi overlay.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+ write_bitstream -force overlay.bit
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+ catch {write_debug_probes -quiet -force overlay}
+ catch {file copy -force overlay.ltx debug_nets.ltx}
+ close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+ step_failed write_bitstream
+ return -code error $RESULT
+} else {
+ end_step write_bitstream
+ unset ACTIVE_STEP
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/rtl-proj/rtl.runs/impl_1/overlay.vdi b/rtl-proj/rtl.runs/impl_1/overlay.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..3b39557c6f003605f6623fbfd5d7e697db86d213
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay.vdi
@@ -0,0 +1,686 @@
+#-----------------------------------------------------------
+# Vivado v2020.2 (64-bit)
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+# Start of session at: Fri Jun 4 02:05:15 2021
+# Process ID: 1655663
+# Current directory: /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1
+# Command line: vivado -log overlay.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source overlay.tcl -notrace
+# Log file: /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay.vdi
+# Journal file: /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/vivado.jou
+#-----------------------------------------------------------
+source overlay.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/mh02127/pixel_manipulation/embedded-security-project/hls-proj'.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
+Command: link_design -top overlay -part xc7z020clg400-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7z020clg400-1
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.dcp' for cell 'axi_dma_0'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_pixel_0/overlay_pixel_0.dcp' for cell 'pixel'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_ps_0/overlay_ps_0.dcp' for cell 'ps'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0.dcp' for cell 'rst_ps_50M'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_xbar_1/overlay_xbar_1.dcp' for cell 'axi_mem_intercon/xbar'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_pc_1/overlay_auto_pc_1.dcp' for cell 'axi_mem_intercon/m00_couplers/auto_pc'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_0/overlay_auto_us_0.dcp' for cell 'axi_mem_intercon/s00_couplers/auto_us'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_1/overlay_auto_us_1.dcp' for cell 'axi_mem_intercon/s01_couplers/auto_us'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_xbar_0/overlay_xbar_0.dcp' for cell 'ps_axi_periph/xbar'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_pc_0/overlay_auto_pc_0.dcp' for cell 'ps_axi_periph/s00_couplers/auto_pc'
+Netlist sorting complete. Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2288.238 ; gain = 0.000 ; free physical = 194621 ; free virtual = 207057
+INFO: [Netlist 29-17] Analyzing 108 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2020.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_ps_0/overlay_ps_0.xdc] for cell 'ps/inst'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_ps_0/overlay_ps_0.xdc] for cell 'ps/inst'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc] for cell 'axi_dma_0/U0'
+WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc:52]
+WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc:56]
+WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc:61]
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc] for cell 'axi_dma_0/U0'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0_board.xdc] for cell 'rst_ps_50M/U0'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0_board.xdc] for cell 'rst_ps_50M/U0'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0.xdc] for cell 'rst_ps_50M/U0'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0.xdc] for cell 'rst_ps_50M/U0'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0_clocks.xdc] for cell 'axi_dma_0/U0'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0_clocks.xdc] for cell 'axi_dma_0/U0'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_0/overlay_auto_us_0_clocks.xdc] for cell 'axi_mem_intercon/s00_couplers/auto_us/inst'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_0/overlay_auto_us_0_clocks.xdc] for cell 'axi_mem_intercon/s00_couplers/auto_us/inst'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_1/overlay_auto_us_1_clocks.xdc] for cell 'axi_mem_intercon/s01_couplers/auto_us/inst'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_1/overlay_auto_us_1_clocks.xdc] for cell 'axi_mem_intercon/s01_couplers/auto_us/inst'
+INFO: [Project 1-1715] 2 XPM XDC files have been applied to the design.
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2512.176 ; gain = 0.000 ; free physical = 193243 ; free virtual = 205679
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 5 instances were transformed.
+ RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 4 instances
+ RAM32X1D => RAM32X1D (RAMD32(x2)): 1 instance
+
+21 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2512.176 ; gain = 224.109 ; free physical = 193243 ; free virtual = 205679
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2512.176 ; gain = 0.000 ; free physical = 193984 ; free virtual = 206421
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 140cee8b3
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2650.078 ; gain = 137.902 ; free physical = 193614 ; free virtual = 206050
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 2 inverter(s) to 6 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 18b3a15e5
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193446 ; free virtual = 205882
+INFO: [Opt 31-389] Phase Retarget created 9 cells and removed 86 cells
+INFO: [Opt 31-1021] In phase Retarget, 24 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 2 inverter(s) to 9 load pin(s).
+Phase 2 Constant propagation | Checksum: 2242e1256
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193446 ; free virtual = 205882
+INFO: [Opt 31-389] Phase Constant propagation created 260 cells and removed 758 cells
+INFO: [Opt 31-1021] In phase Constant propagation, 24 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 1fc269322
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193442 ; free virtual = 205878
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 262 cells
+INFO: [Opt 31-1021] In phase Sweep, 96 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 1fc269322
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193428 ; free virtual = 205864
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 1fc269322
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193422 ; free virtual = 205859
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 1fc269322
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193419 ; free virtual = 205856
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+INFO: [Opt 31-1021] In phase Post Processing Netlist, 33 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 9 | 86 | 24 |
+| Constant propagation | 260 | 758 | 24 |
+| Sweep | 0 | 262 | 96 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 33 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193405 ; free virtual = 205841
+Ending Logic Optimization Task | Checksum: 1aebeab42
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193404 ; free virtual = 205841
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+INFO: [Pwropt 34-9] Applying IDT optimizations ...
+INFO: [Pwropt 34-10] Applying ODC optimizations ...
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+
+
+Starting PowerOpt Patch Enables Task
+INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 2 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
+INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
+Number of BRAM Ports augmented: 3 newly gated: 0 Total Ports: 4
+Ending PowerOpt Patch Enables Task | Checksum: 14bf263f5
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193367 ; free virtual = 205803
+Ending Power Optimization Task | Checksum: 14bf263f5
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3123.039 ; gain = 302.023 ; free physical = 193374 ; free virtual = 205810
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 14bf263f5
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193374 ; free virtual = 205810
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193374 ; free virtual = 205810
+Ending Netlist Obfuscation Task | Checksum: 19bdfcc68
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193374 ; free virtual = 205810
+INFO: [Common 17-83] Releasing license: Implementation
+47 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 3123.039 ; gain = 610.863 ; free physical = 193374 ; free virtual = 205810
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193366 ; free virtual = 205805
+INFO: [Common 17-1381] The checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file overlay_drc_opted.rpt -pb overlay_drc_opted.pb -rpx overlay_drc_opted.rpx
+Command: report_drc -file overlay_drc_opted.rpt -pb overlay_drc_opted.pb -rpx overlay_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Coretcl 2-168] The results of DRC are in file /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193267 ; free virtual = 205707
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c4dde10d
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193267 ; free virtual = 205707
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193267 ; free virtual = 205707
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 63597b98
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193292 ; free virtual = 205731
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: eab7f8df
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193293 ; free virtual = 205733
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: eab7f8df
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193293 ; free virtual = 205733
+Phase 1 Placer Initialization | Checksum: eab7f8df
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193292 ; free virtual = 205732
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 15eb4b930
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193276 ; free virtual = 205715
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: cdac8491
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193276 ; free virtual = 205716
+
+Phase 2.3 Global Placement Core
+
+Phase 2.3.1 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 349 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-775] End 1 Pass. Optimized 116 nets or cells. Created 0 new cell, deleted 116 existing cells and moved 0 existing cell
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193229 ; free virtual = 205668
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 116 | 116 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 116 | 116 | 0 | 3 | 00:00:01 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.3.1 Physical Synthesis In Placer | Checksum: 21643c6ce
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193227 ; free virtual = 205666
+Phase 2.3 Global Placement Core | Checksum: 13c2aa124
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193226 ; free virtual = 205665
+Phase 2 Global Placement | Checksum: 13c2aa124
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193226 ; free virtual = 205665
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 1ce0828fc
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:10 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193229 ; free virtual = 205669
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13619352c
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193224 ; free virtual = 205664
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1953488eb
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193224 ; free virtual = 205663
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 1f3f6e0cc
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193225 ; free virtual = 205664
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1539ebf56
+
+Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193385 ; free virtual = 205825
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: edf85c0a
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193377 ; free virtual = 205817
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 119290a8c
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193376 ; free virtual = 205816
+Phase 3 Detail Placement | Checksum: 119290a8c
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193375 ; free virtual = 205815
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 1b524cb9c
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.922 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 21ce08e3a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193306 ; free virtual = 205746
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
+Ending Physical Synthesis Task | Checksum: 23e1a9a2d
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.38 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193328 ; free virtual = 205768
+Phase 4.1.1.1 BUFG Insertion | Checksum: 1b524cb9c
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193339 ; free virtual = 205779
+INFO: [Place 30-746] Post Placement Timing Summary WNS=9.922. For the most accurate timing information please run report_timing.
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193359 ; free virtual = 205799
+Phase 4.1 Post Commit Optimization | Checksum: 19d0c2147
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193380 ; free virtual = 205820
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 19d0c2147
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 19d0c2147
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+Phase 4.3 Placer Reporting | Checksum: 19d0c2147
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: ce76e94c
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193382 ; free virtual = 205822
+Ending Placer Task | Checksum: 988376d7
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193381 ; free virtual = 205821
+INFO: [Common 17-83] Releasing license: Implementation
+82 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193404 ; free virtual = 205844
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.60 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193345 ; free virtual = 205797
+INFO: [Common 17-1381] The checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file overlay_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193347 ; free virtual = 205792
+INFO: [runtcl-4] Executing : report_utilization -file overlay_utilization_placed.rpt -pb overlay_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file overlay_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193398 ; free virtual = 205842
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+91 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193306 ; free virtual = 205761
+INFO: [Common 17-1381] The checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+Checksum: PlaceDB: 6f4628bd ConstDB: 0 ShapeSum: 293d4e1a RouteDB: 0
+
+Phase 1 Build RT Design
+Phase 1 Build RT Design | Checksum: 78af158c
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193308 ; free virtual = 205756
+Post Restoration Checksum: NetGraph: 41792313 NumContArr: 3735f279 Constraints: 0 Timing: 0
+
+Phase 2 Router Initialization
+
+Phase 2.1 Create Timer
+Phase 2.1 Create Timer | Checksum: 78af158c
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193310 ; free virtual = 205758
+
+Phase 2.2 Fix Topology Constraints
+Phase 2.2 Fix Topology Constraints | Checksum: 78af158c
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193276 ; free virtual = 205725
+
+Phase 2.3 Pre Route Cleanup
+Phase 2.3 Pre Route Cleanup | Checksum: 78af158c
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193276 ; free virtual = 205725
+ Number of Nodes with overlaps = 0
+
+Phase 2.4 Update Timing
+Phase 2.4 Update Timing | Checksum: a307ef69
+
+Time (s): cpu = 00:00:36 ; elapsed = 00:00:25 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 194006 ; free virtual = 206454
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=10.154 | TNS=0.000 | WHS=-0.329 | THS=-106.612|
+
+Phase 2 Router Initialization | Checksum: 3e4bd552
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:26 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193996 ; free virtual = 206444
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 6305
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 6305
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: 3e4bd552
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:26 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193990 ; free virtual = 206438
+Phase 3 Initial Routing | Checksum: 15ea02df4
+
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:27 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193957 ; free virtual = 206406
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 319
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.581 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 4.1 Global Iteration 0 | Checksum: 250dc868f
+
+Time (s): cpu = 00:00:49 ; elapsed = 00:00:29 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193972 ; free virtual = 206420
+
+Phase 4.2 Global Iteration 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.581 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 4.2 Global Iteration 1 | Checksum: f81c4f55
+
+Time (s): cpu = 00:00:50 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193961 ; free virtual = 206409
+Phase 4 Rip-up And Reroute | Checksum: f81c4f55
+
+Time (s): cpu = 00:00:50 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193961 ; free virtual = 206409
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+
+Phase 5.1.1 Update Timing
+Phase 5.1.1 Update Timing | Checksum: 124afa862
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193960 ; free virtual = 206408
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.581 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Delay CleanUp | Checksum: 124afa862
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193960 ; free virtual = 206408
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: 124afa862
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193960 ; free virtual = 206408
+Phase 5 Delay and Skew Optimization | Checksum: 124afa862
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193960 ; free virtual = 206408
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 101bfc817
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193956 ; free virtual = 206404
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.581 | TNS=0.000 | WHS=0.030 | THS=0.000 |
+
+Phase 6.1 Hold Fix Iter | Checksum: 16a9da8f8
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193956 ; free virtual = 206404
+Phase 6 Post Hold Fix | Checksum: 16a9da8f8
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193956 ; free virtual = 206404
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 1.04857 %
+ Global Horizontal Routing Utilization = 1.19244 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 7 Route finalize | Checksum: fcdb8667
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193955 ; free virtual = 206403
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: fcdb8667
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193954 ; free virtual = 206402
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: f5fb06ba
+
+Time (s): cpu = 00:00:57 ; elapsed = 00:00:32 . Memory (MB): peak = 3138.941 ; gain = 15.902 ; free physical = 193955 ; free virtual = 206403
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=9.581 | TNS=0.000 | WHS=0.030 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: f5fb06ba
+
+Time (s): cpu = 00:00:57 ; elapsed = 00:00:32 . Memory (MB): peak = 3138.941 ; gain = 15.902 ; free physical = 193956 ; free virtual = 206404
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:57 ; elapsed = 00:00:32 . Memory (MB): peak = 3138.941 ; gain = 15.902 ; free physical = 193993 ; free virtual = 206441
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+107 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:01:05 ; elapsed = 00:00:35 . Memory (MB): peak = 3138.941 ; gain = 15.902 ; free physical = 193993 ; free virtual = 206441
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 3138.941 ; gain = 0.000 ; free physical = 193965 ; free virtual = 206427
+INFO: [Common 17-1381] The checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file overlay_drc_routed.rpt -pb overlay_drc_routed.pb -rpx overlay_drc_routed.rpx
+Command: report_drc -file overlay_drc_routed.rpt -pb overlay_drc_routed.pb -rpx overlay_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Coretcl 2-168] The results of DRC are in file /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file overlay_methodology_drc_routed.rpt -pb overlay_methodology_drc_routed.pb -rpx overlay_methodology_drc_routed.rpx
+Command: report_methodology -file overlay_methodology_drc_routed.rpt -pb overlay_methodology_drc_routed.pb -rpx overlay_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file overlay_power_routed.rpt -pb overlay_power_summary_routed.pb -rpx overlay_power_routed.rpx
+Command: report_power -file overlay_power_routed.rpt -pb overlay_power_summary_routed.pb -rpx overlay_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
+Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
+119 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file overlay_route_status.rpt -pb overlay_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file overlay_timing_summary_routed.rpt -pb overlay_timing_summary_routed.pb -rpx overlay_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [runtcl-4] Executing : report_incremental_reuse -file overlay_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file overlay_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file overlay_bus_skew_routed.rpt -pb overlay_bus_skew_routed.pb -rpx overlay_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Memdata 28-167] Found XPM memory block axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
+INFO: [Memdata 28-208] The XPM instance: <axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <axi_dma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
+INFO: [Memdata 28-208] The XPM instance: <axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <axi_dma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
+Command: write_bitstream -force overlay.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+WARNING: [DRC RTSTAT-10] No routable loads: 33 net(s) have no routable loads. The problem bus(es) and/or net(s) are axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0], axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0], axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0]... and (the first 15 of 21 listed).
+INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
+INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 2 Advisories
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./overlay.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
+INFO: [Common 17-83] Releasing license: Implementation
+17 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 3491.031 ; gain = 235.531 ; free physical = 193076 ; free virtual = 205537
+INFO: [Common 17-206] Exiting Vivado at Fri Jun 4 02:07:52 2021...
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.pb b/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..fbaf2022eff143581438dd065180cc4408a29770
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.rpt
@@ -0,0 +1,15 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:07:24 2021
+| Host : joan running 64-bit unknown
+| Command : report_bus_skew -warn_on_violation -file overlay_bus_skew_routed.rpt -pb overlay_bus_skew_routed.pb -rpx overlay_bus_skew_routed.rpx
+| Design : overlay
+| Device : 7z020-clg400
+| Speed File : -1 PRODUCTION 1.12 2019-11-22
+------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.rpx b/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..4f06669cac01722c04c3ed156b4cb562718eb925
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_bus_skew_routed.rpx differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_clock_utilization_routed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_clock_utilization_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..c148117497119e702aceee0cc511f41be98f2f44
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_clock_utilization_routed.rpt
@@ -0,0 +1,201 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:07:23 2021
+| Host : joan running 64-bit unknown
+| Command : report_clock_utilization -file overlay_clock_utilization_routed.rpt
+| Design : overlay
+| Device : 7z020-clg400
+| Speed File : -1 PRODUCTION 1.12 2019-11-22
+| Design State : Routed
+-------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Device Cell Placement Summary for Global Clock g0
+7. Clock Region Cell Placement per Global Clock: Region X0Y0
+8. Clock Region Cell Placement per Global Clock: Region X1Y0
+9. Clock Region Cell Placement per Global Clock: Region X0Y1
+10. Clock Region Cell Placement per Global Clock: Region X1Y1
+11. Clock Region Cell Placement per Global Clock: Region X0Y2
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
+| BUFH | 0 | 72 | 0 | 0 | 0 |
+| BUFIO | 0 | 16 | 0 | 0 | 0 |
+| BUFMR | 0 | 8 | 0 | 0 | 0 |
+| BUFR | 0 | 16 | 0 | 0 | 0 |
+| MMCM | 0 | 4 | 0 | 0 | 0 |
+| PLL | 0 | 4 | 0 | 0 | 0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------+---------------------------------------------+-------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------+---------------------------------------------+-------------------+
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 5 | 4371 | 0 | 20.000 | clk_fpga_0 | ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O | ps/inst/FCLK_CLK0 |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------+---------------------------------------------+-------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+--------------------------+--------------------------------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+--------------------------+--------------------------------+
+| src0 | g0 | PS7/FCLKCLK[0] | PS7_X0Y0 | PS7_X0Y0 | X0Y2 | 1 | 0 | 20.000 | clk_fpga_0 | ps/inst/PS7_i/FCLKCLK[0] | ps/inst/FCLK_CLK_unbuffered[0] |
++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+--------------------------+--------------------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1947 | 2500 | 941 | 1000 | 0 | 60 | 2 | 30 | 0 | 60 |
+| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 42 | 3200 | 12 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
+| X0Y1 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1865 | 1200 | 844 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 97 | 2600 | 13 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
+| X0Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 124 | 1200 | 52 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+| | X0 | X1 |
++----+----+----+
+| Y2 | 1 | 0 |
+| Y1 | 1 | 1 |
+| Y0 | 1 | 1 |
++----+----+----+
+
+
+6. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
+| g0 | BUFG/O | n/a | clk_fpga_0 | 20.000 | {0.000 10.000} | 4363 | 0 | 0 | 0 | ps/inst/FCLK_CLK0 |
++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+-------+-----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+-------+-----+-----------------------+
+| Y2 | 143 | 0 | 0 |
+| Y1 | 1997 | 97 | 0 |
+| Y0 | 2084 | 42 | 0 |
++----+-------+-----+-----------------------+
+
+
+7. Clock Region Cell Placement per Global Clock: Region X0Y0
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------+
+| g0 | n/a | BUFG/O | None | 2084 | 0 | 1947 | 135 | 2 | 0 | 0 | 0 | 0 | 0 | ps/inst/FCLK_CLK0 |
++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+8. Clock Region Cell Placement per Global Clock: Region X1Y0
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
+| g0 | n/a | BUFG/O | None | 42 | 0 | 42 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ps/inst/FCLK_CLK0 |
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+9. Clock Region Cell Placement per Global Clock: Region X0Y1
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------+
+| g0 | n/a | BUFG/O | None | 1997 | 0 | 1865 | 132 | 0 | 0 | 0 | 0 | 0 | 0 | ps/inst/FCLK_CLK0 |
++-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+10. Clock Region Cell Placement per Global Clock: Region X1Y1
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
+| g0 | n/a | BUFG/O | None | 97 | 0 | 97 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ps/inst/FCLK_CLK0 |
++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+11. Clock Region Cell Placement per Global Clock: Region X0Y2
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+
+| g0 | n/a | BUFG/O | None | 143 | 0 | 124 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | ps/inst/FCLK_CLK0 |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------+
+* Clock Loads column represents the clock pin loads (pin count)
+** Non-Clock Loads column represents the non-clock pin loads (pin count)
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives
+set_property LOC BUFGCTRL_X0Y16 [get_cells ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+
+# Clock net "ps/inst/FCLK_CLK0" driven by instance "ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG" located at site "BUFGCTRL_X0Y16"
+#startgroup
+create_pblock {CLKAG_ps/inst/FCLK_CLK0}
+add_cells_to_pblock [get_pblocks {CLKAG_ps/inst/FCLK_CLK0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ps/inst/FCLK_CLK0"}]]]
+resize_pblock [get_pblocks {CLKAG_ps/inst/FCLK_CLK0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
+#endgroup
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_control_sets_placed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..389538464b1db9da3c051b0c0f5946615775e8f0
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_control_sets_placed.rpt
@@ -0,0 +1,290 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:06:33 2021
+| Host : joan running 64-bit unknown
+| Command : report_control_sets -verbose -file overlay_control_sets_placed.rpt
+| Design : overlay
+| Device : xc7z020
+------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+| Status | Count |
++----------------------------------------------------------+-------+
+| Total control sets | 212 |
+| Minimum number of control sets | 212 |
+| Addition due to synthesis replication | 0 |
+| Addition due to physical synthesis replication | 0 |
+| Unused register locations in slices containing registers | 613 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+| Fanout | Count |
++--------------------+-------+
+| Total control sets | 212 |
+| >= 0 to < 4 | 11 |
+| >= 4 to < 6 | 39 |
+| >= 6 to < 8 | 14 |
+| >= 8 to < 10 | 26 |
+| >= 10 to < 12 | 12 |
+| >= 12 to < 14 | 14 |
+| >= 14 to < 16 | 9 |
+| >= 16 | 87 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No | No | No | 365 | 143 |
+| No | No | Yes | 42 | 14 |
+| No | Yes | No | 444 | 192 |
+| Yes | No | No | 1107 | 303 |
+| Yes | No | Yes | 60 | 13 |
+| Yes | Yes | No | 2057 | 589 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_ld_cmd | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 1 | 1 | 1.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/push | | 1 | 1 | 1.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/FSM_sequential_state_reg[0]_1 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/FSM_sequential_state_reg[0]_0 | 1 | 1 | 1.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/push | | 1 | 1 | 1.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/push | | 1 | 1 | 1.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_wr_fifo | | 1 | 2 | 2.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/sel | | 1 | 2 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 1 | 2 | 2.00 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/rst_i | 1 | 3 | 3.00 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_dout_V_keep_V_U/B_V_data_1_payload_A[3]_i_1__2_n_0 | | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/E[0] | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/grant_hot | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/grant_hot | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/E[0] | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_axi_arready_2 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/FSM_sequential_state_reg[1]_0 | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/SR[0] | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/b.b_pipe/p_1_in | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/b.b_pipe/p_0_in | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/m_axi_awready_0[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/pushed_commands[3]_i_1_n_0 | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_dout_V_keep_V_U/B_V_data_1_load_B | | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/aresetn_d_reg[0]_0 | 3 | 4 | 1.33 |
+| ps/inst/FCLK_CLK0 | | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/aresetn_d_reg[1]_inv_0 | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_din_V_keep_V_U/B_V_data_1_payload_A[3]_i_1__0_n_0 | | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_din_V_keep_V_U/B_V_data_1_load_B | | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/sig_token_cntr[3]_i_1_n_0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SS[0] | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/m_valid_i | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.si_transactor_aw/gen_single_thread.accept_cnt[3]_i_1__0_n_0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_single_thread.accept_cnt[3]_i_1_n_0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | | rst_ps_50M/U0/EXT_LPF/lpf_int | 3 | 4 | 1.33 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/pushed_commands[3]_i_1__0_n_0 | 2 | 4 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[1].gen_si_write.wdata_router_w/wrouter_aw_fifo/SS[0] | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_push_coelsc_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/sig_coelsc_cmd_cmplt_reg_i_1_n_0 | 1 | 4 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_STATUS_CNTLR/sig_push_rd_sts_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_STATUS_CNTLR/sig_rd_sts_interr_reg_i_1_n_0 | 1 | 5 | 5.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 1 | 5 | 5.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 5 | 2.50 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 1 | 5 | 5.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/cnt_read[4]_i_1_n_0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 2 | 5 | 2.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 5 | 2.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 5 | 2.50 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/s_axi_aresetn | 1 | 5 | 5.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_ADDR.addr_q | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 2 | 5 | 2.50 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read[4]_i_1__0_n_0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 2 | 5 | 2.50 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/E[0] | | 2 | 5 | 2.50 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 5 | 1.67 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 1 | 5 | 5.00 |
+| ps/inst/FCLK_CLK0 | rst_ps_50M/U0/SEQ/seq_cnt_en | rst_ps_50M/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | 6.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_data_inst/m_axi_wready_0[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/SR[0] | 2 | 6 | 3.00 |
+| ps/inst/FCLK_CLK0 | pixel/inst/control_s_axi_U/waddr | | 1 | 6 | 6.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/SR[0] | 2 | 6 | 3.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/empty_fwft_i_reg[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/SR[0] | 2 | 6 | 3.00 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_2 | 2 | 6 | 3.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 3 | 7 | 2.33 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/SR[0] | 3 | 7 | 2.33 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/p_15_in | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/s_axi_aresetn | 3 | 7 | 2.33 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/s_axi_aresetn | 2 | 7 | 3.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_MM2S_SMPL_SM/mm2s_all_idle | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/s_soft_reset_i_re | 2 | 7 | 3.50 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/s_axi_wvalid_0[0] | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 3 | 7 | 2.33 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/s2mm_all_idle | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/s_soft_reset_i_re | 1 | 7 | 7.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/sig_clr_dbc_reg_reg_0[0] | 4 | 7 | 1.75 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/gen_axi.read_cnt[7]_i_1_n_0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 4 | 8 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 2 | 8 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 2 | 8 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 3 | 8 | 2.67 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 8 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 3 | 8 | 2.67 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 3 | 8 | 2.67 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/SR[0] | 2 | 8 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 3 | 8 | 2.67 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 3 | 8 | 2.67 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 | 2 | 8 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 1 | 8 | 8.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 3 | 8 | 2.67 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SS[0] | 3 | 8 | 2.67 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12][0] | 3 | 8 | 2.67 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | | 1 | 8 | 8.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[0]_0[0] | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/SS[0] | 2 | 8 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 9 | 3.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 2 | 9 | 4.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_last_dbeat_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_cmd_stat_rst_user_reg_n_cdc_from_reg | 4 | 9 | 2.25 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 2 | 9 | 4.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_valid_fifo_ld12_out | | 3 | 9 | 3.00 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 9 | 3.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | | 2 | 9 | 4.50 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/pop_mi_data | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/s_axi_aresetn | 4 | 9 | 2.25 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]_0 | 2 | 10 | 5.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arvalid_re | axi_dma_0/U0/I_RST_MODULE/SR[0] | 3 | 10 | 3.33 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 3 | 10 | 3.33 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 10 | 3.33 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ram_empty_fb_i_reg[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 2 | 10 | 5.00 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_1[0] | 2 | 10 | 5.00 |
+| ps/inst/FCLK_CLK0 | | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 6 | 10 | 1.67 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 2 | 10 | 5.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]_0 | 2 | 10 | 5.00 |
+| ps/inst/FCLK_CLK0 | | ps_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0] | 5 | 11 | 2.20 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/sel_first_reg[0] | | 4 | 12 | 3.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg_ns | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 6 | 12 | 2.00 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]_0 | 4 | 12 | 3.00 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 3 | 12 | 4.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/incr_cmd_0/axaddr_incr[11]_i_1_n_0 | | 2 | 12 | 6.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/m_valid_i_reg[0] | | 5 | 12 | 2.40 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/E[0] | | 4 | 12 | 3.00 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0] | 4 | 12 | 3.00 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0 | 6 | 13 | 2.17 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 5 | 13 | 2.60 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/r_push_r | | 4 | 13 | 3.25 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[0]_0[0] | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/halted1 | 8 | 13 | 1.62 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 6 | 13 | 2.17 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[12]_0[0] | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/halted1 | 5 | 13 | 2.60 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/halted1 | 7 | 14 | 2.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/s_ready_i_reg_0 | | 4 | 14 | 3.50 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/p_1_in | | 3 | 14 | 4.67 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/enb | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 4 | 14 | 3.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_next_sequential_reg_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/m_axi_mm2s_rlast_0 | 3 | 14 | 4.67 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 14 | 2.80 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 6 | 15 | 2.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/FSM_sequential_gen_fwft.curr_fwft_state_reg[1] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/Q[0] | 5 | 15 | 3.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_calc2_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 2 | 15 | 7.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[0]_i_1_n_0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_msh[0]_i_1_n_0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/E[0] | | 2 | 16 | 8.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_im0_msh[0]_i_1_n_0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 4 | 16 | 4.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/m_axi_awready_0 | | 3 | 16 | 5.33 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RD_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 3 | 16 | 5.33 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[25]_i_1_n_0 | 5 | 18 | 3.60 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 5 | 20 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/M_READY_I | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/s_axi_aresetn | 6 | 21 | 3.50 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_axi_arready_2 | | 8 | 21 | 2.62 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/valid_Write | | 6 | 22 | 3.67 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/M_READY_I | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 7 | 23 | 3.29 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/FSM_sequential_state_reg[0]_1 | | 12 | 24 | 2.00 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/SR[0] | 13 | 24 | 1.85 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/s_axi_aresetn | 11 | 24 | 2.18 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_RST_MODULE/SR[0] | 10 | 25 | 2.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_sm_ld_xfer_reg_ns | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 8 | 25 | 3.12 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[25]_i_1_n_0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 7 | 26 | 3.71 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[22]_0[0] | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/halted1 | 8 | 26 | 3.25 |
+| ps/inst/FCLK_CLK0 | | pixel/inst/control_s_axi_U/ap_rst_n_inv | 11 | 26 | 2.36 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/E[0] | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/halted1 | 8 | 26 | 3.25 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/p_0_in1_in | ps_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0] | 11 | 26 | 2.36 |
+| ps/inst/FCLK_CLK0 | | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 13 | 28 | 2.15 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_push_to_wsc_reg | | 4 | 29 | 7.25 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 4 | 29 | 7.25 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_push_regfifo | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 5 | 31 | 6.20 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 7 | 31 | 4.43 |
+| ps/inst/FCLK_CLK0 | pixel/inst/control_s_axi_U/ar_hs | pixel/inst/control_s_axi_U/rdata[31]_i_1_n_0 | 12 | 32 | 2.67 |
+| ps/inst/FCLK_CLK0 | pixel/inst/control_s_axi_U/int_w | pixel/inst/control_s_axi_U/ap_rst_n_inv | 5 | 32 | 6.40 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_load_B | | 8 | 32 | 4.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | | 13 | 32 | 2.46 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[6]_0[0] | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/halted1 | 11 | 32 | 2.91 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_push_input_reg11_out | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 9 | 32 | 3.56 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[31]_i_1__0_n_0 | | 6 | 32 | 5.33 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_load_B | | 9 | 32 | 3.56 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A[31]_i_1_n_0 | | 11 | 32 | 2.91 |
+| ps/inst/FCLK_CLK0 | pixel/inst/control_s_axi_U/int_len_i | pixel/inst/control_s_axi_U/ap_rst_n_inv | 6 | 32 | 5.33 |
+| ps/inst/FCLK_CLK0 | pixel/inst/regslice_both_din_V_data_V_U/din_TREADY_int_regslice | pixel/inst/control_s_axi_U/ap_rst_n_inv | 9 | 32 | 3.56 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_WRITE.axi2ip_wrce_reg[18]_0[0] | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/halted1 | 9 | 32 | 3.56 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_SYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 16 | 32 | 2.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | | 10 | 32 | 3.20 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | | 7 | 32 | 4.57 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | | 10 | 32 | 3.20 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/m_axi_awready_0[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/SR[0] | 9 | 33 | 3.67 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_reg[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_empty_i_1_n_0 | 7 | 33 | 4.71 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SS[0] | 13 | 34 | 2.62 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/wr_en0 | | 9 | 34 | 3.78 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_init_reg_reg_0 | 15 | 35 | 2.33 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_push_input_reg14_out | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/sig_input_cache_type_reg0 | 10 | 35 | 3.50 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/E[0] | | 15 | 35 | 2.33 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/SR[0] | 8 | 36 | 4.50 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out0 | 14 | 37 | 2.64 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 12 | 37 | 3.08 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_s_ready_dup | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SS[0] | 7 | 37 | 5.29 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out_en | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/ENABLE_AXIS_SKID.I_MM2S_SKID_BUF/sig_data_reg_out0 | 12 | 37 | 3.08 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 5 | 39 | 7.80 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/FIFO_Full_reg | | 5 | 40 | 8.00 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/ar.ar_pipe/E[0] | | 14 | 40 | 2.86 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/p_1_in | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 11 | 41 | 3.73 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 14 | 41 | 2.93 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_s_ready_dup | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 13 | 41 | 3.15 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 9 | 41 | 4.56 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0 | 10 | 41 | 4.10 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s01_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/si_register_slice_inst/aw.aw_pipe/E[0] | | 11 | 41 | 3.73 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/SR[0] | 7 | 42 | 6.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_MSTR_PCC/sig_addr_cntr_lsh_im0[15]_i_1_n_0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_init_reg_reg_0 | 13 | 42 | 3.23 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_halt_reg_reg | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg[31]_i_1_n_0 | 6 | 42 | 7.00 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg[31]_i_1__0_n_0 | 7 | 43 | 6.14 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/p_1_in | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/SR[0] | 11 | 44 | 4.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/s_ready_i_reg_0 | | 12 | 47 | 3.92 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/p_1_in | | 11 | 47 | 4.27 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/s_ready_i_reg_0 | | 9 | 48 | 5.33 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_ready_i_reg_0 | | 12 | 48 | 4.00 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | | 10 | 48 | 4.80 |
+| ps/inst/FCLK_CLK0 | ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_valid_i_reg[0] | | 9 | 48 | 5.33 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/GEN_INDET_BTT.lsig_absorb2tlast_reg | 16 | 52 | 3.25 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data[66]_i_1_n_0 | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0 | 14 | 59 | 4.21 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_MM2S_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data[66]_i_1__0_n_0 | axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_MM2S.RESET_I/GNE_SYNC_RESET.scndry_resetn_reg_0 | 14 | 59 | 4.21 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_push_regfifo | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 13 | 60 | 4.62 |
+| ps/inst/FCLK_CLK0 | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/E[0] | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/I_RESET/SS[0] | 15 | 60 | 4.00 |
+| ps/inst/FCLK_CLK0 | | axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 34 | 63 | 1.85 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/E[0] | axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/SR[0] | 17 | 65 | 3.82 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_read.si_transactor_ar/E[0] | | 15 | 67 | 4.47 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r.r_pipe/s_ready_i_reg_0 | | 16 | 67 | 4.19 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.read_data_inst/E[0] | | 19 | 67 | 3.53 |
+| ps/inst/FCLK_CLK0 | axi_mem_intercon/s00_couplers/auto_us/inst/gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/s_ready_i_reg_0 | | 19 | 67 | 3.53 |
+| ps/inst/FCLK_CLK0 | | | 144 | 366 | 2.54 |
++--------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.pb b/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..1de10e80b98d1d0715d2fafbb53606d67ed9d975
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.rpt b/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..f79d111812c7dc0be60d52efa9991000d2e78d4c
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.rpt
@@ -0,0 +1,46 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:06:12 2021
+| Host : joan running 64-bit unknown
+| Command : report_drc -file overlay_drc_opted.rpt -pb overlay_drc_opted.pb -rpx overlay_drc_opted.rpx
+| Design : overlay
+| Device : xc7z020clg400-1
+| Speed File : -1
+| Design State : Synthesized
+------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 2
++----------+----------+-------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-------------+------------+
+| REQP-181 | Advisory | writefirst | 2 |
++----------+----------+-------------+------------+
+
+2. REPORT DETAILS
+-----------------
+REQP-181#1 Advisory
+writefirst
+Synchronous clocking is detected for BRAM (axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
+Related violations: <none>
+
+REQP-181#2 Advisory
+writefirst
+Synchronous clocking is detected for BRAM (axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
+Related violations: <none>
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.rpx b/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..da980ecd6ec5e88b9083729d6d95c36d2307de68
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.rpx differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.pb b/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..b3fe52a95dcb20d701ea36cd71f9f112f55bb482
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..0555f46af20f0f304c5b8469fd9c46b03a849da0
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.rpt
@@ -0,0 +1,67 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:07:17 2021
+| Host : joan running 64-bit unknown
+| Command : report_drc -file overlay_drc_routed.rpt -pb overlay_drc_routed.pb -rpx overlay_drc_routed.rpx
+| Design : overlay
+| Device : xc7z020clg400-1
+| Speed File : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 3
++-----------+----------+-------------------+------------+
+| Rule | Severity | Description | Violations |
++-----------+----------+-------------------+------------+
+| RTSTAT-10 | Warning | No routable loads | 1 |
+| REQP-181 | Advisory | writefirst | 2 |
++-----------+----------+-------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+RTSTAT-10#1 Warning
+No routable loads
+33 net(s) have no routable loads. The problem bus(es) and/or net(s) are axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0],
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0],
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0]
+ (the first 15 of 21 listed).
+Related violations: <none>
+
+REQP-181#1 Advisory
+writefirst
+Synchronous clocking is detected for BRAM (axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
+Related violations: <none>
+
+REQP-181#2 Advisory
+writefirst
+Synchronous clocking is detected for BRAM (axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
+Related violations: <none>
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.rpx b/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..bb434d03a38af93db26332edb06adbb2a91d7956
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.rpx differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_io_placed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..6cc886de230e90bce45e84bd3ae7859b7e5257c6
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_io_placed.rpt
@@ -0,0 +1,442 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:06:33 2021
+| Host : joan running 64-bit unknown
+| Command : report_io -file overlay_io_placed.rpt
+| Design : overlay
+| Device : xc7z020
+| Speed File : -1
+| Package : clg400
+| Package Version : FINAL 2012-06-26
+| Package Pin Delay Version : VERS. 2.0 2012-06-26
+-------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+| 130 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+-------------------+------------+-------------------------+-------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------------+------------+-------------------------+-------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | DDR_dm[0] | | PS_DDR_DM0_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| A2 | DDR_dq[2] | | PS_DDR_DQ2_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| A4 | DDR_dq[3] | | PS_DDR_DQ3_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| A5 | FIXED_IO_mio[6] | | PS_MIO6_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A6 | FIXED_IO_mio[5] | | PS_MIO5_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A7 | FIXED_IO_mio[1] | | PS_MIO1_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A9 | FIXED_IO_mio[43] | | PS_MIO43_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A10 | FIXED_IO_mio[37] | | PS_MIO37_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A11 | FIXED_IO_mio[36] | | PS_MIO36_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A12 | FIXED_IO_mio[34] | | PS_MIO34_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
+| A14 | FIXED_IO_mio[32] | | PS_MIO32_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A15 | FIXED_IO_mio[26] | | PS_MIO26_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A16 | FIXED_IO_mio[24] | | PS_MIO24_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A17 | FIXED_IO_mio[20] | | PS_MIO20_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A19 | FIXED_IO_mio[16] | | PS_MIO16_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| B3 | DDR_dq[1] | | PS_DDR_DQ1_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| B4 | DDR_reset_n | | PS_DDR_DRST_B_502 | INOUT | SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
+| B7 | FIXED_IO_mio[4] | | PS_MIO4_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B8 | FIXED_IO_mio[2] | | PS_MIO2_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B9 | FIXED_IO_mio[51] | | PS_MIO51_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B10 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B12 | FIXED_IO_mio[48] | | PS_MIO48_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B13 | FIXED_IO_mio[50] | | PS_MIO50_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B14 | FIXED_IO_mio[47] | | PS_MIO47_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B15 | FIXED_IO_mio[45] | | PS_MIO45_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
+| B17 | FIXED_IO_mio[22] | | PS_MIO22_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B18 | FIXED_IO_mio[18] | | PS_MIO18_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C1 | DDR_dq[6] | | PS_DDR_DQ6_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| C3 | DDR_dq[0] | | PS_DDR_DQ0_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C5 | FIXED_IO_mio[14] | | PS_MIO14_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C6 | FIXED_IO_mio[11] | | PS_MIO11_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C7 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C8 | FIXED_IO_mio[15] | | PS_MIO15_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C10 | FIXED_IO_mio[52] | | PS_MIO52_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C11 | FIXED_IO_mio[53] | | PS_MIO53_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C12 | FIXED_IO_mio[49] | | PS_MIO49_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C13 | FIXED_IO_mio[29] | | PS_MIO29_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C15 | FIXED_IO_mio[30] | | PS_MIO30_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C16 | FIXED_IO_mio[28] | | PS_MIO28_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C17 | FIXED_IO_mio[41] | | PS_MIO41_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C18 | FIXED_IO_mio[39] | | PS_MIO39_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D1 | DDR_dq[5] | | PS_DDR_DQ5_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| D3 | DDR_dq[4] | | PS_DDR_DQ4_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| D4 | DDR_addr[13] | | PS_DDR_A13_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D5 | FIXED_IO_mio[8] | | PS_MIO8_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D6 | FIXED_IO_mio[3] | | PS_MIO3_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
+| D8 | FIXED_IO_mio[7] | | PS_MIO7_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D9 | FIXED_IO_mio[12] | | PS_MIO12_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D10 | FIXED_IO_mio[19] | | PS_MIO19_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D11 | FIXED_IO_mio[23] | | PS_MIO23_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
+| D13 | FIXED_IO_mio[27] | | PS_MIO27_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D14 | FIXED_IO_mio[40] | | PS_MIO40_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D15 | FIXED_IO_mio[33] | | PS_MIO33_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D16 | FIXED_IO_mio[46] | | PS_MIO46_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E1 | DDR_dq[7] | | PS_DDR_DQ7_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| E2 | DDR_dq[8] | | PS_DDR_DQ8_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| E3 | DDR_dq[9] | | PS_DDR_DQ9_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| E4 | DDR_addr[12] | | PS_DDR_A12_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| E6 | FIXED_IO_mio[0] | | PS_MIO0_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E8 | FIXED_IO_mio[13] | | PS_MIO13_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E9 | FIXED_IO_mio[10] | | PS_MIO10_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | | | |
+| E12 | FIXED_IO_mio[42] | | PS_MIO42_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E13 | FIXED_IO_mio[38] | | PS_MIO38_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E14 | FIXED_IO_mio[17] | | PS_MIO17_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
+| E16 | FIXED_IO_mio[31] | | PS_MIO31_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F1 | DDR_dm[1] | | PS_DDR_DM1_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| F2 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F4 | DDR_addr[14] | | PS_DDR_A14_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| F5 | DDR_addr[10] | | PS_DDR_A10_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| F10 | | | RSVDGND | GND | | | | | | | | | | | | | | | |
+| F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| F12 | FIXED_IO_mio[35] | | PS_MIO35_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| F13 | FIXED_IO_mio[44] | | PS_MIO44_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| F14 | FIXED_IO_mio[21] | | PS_MIO21_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| F15 | FIXED_IO_mio[25] | | PS_MIO25_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| F19 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F20 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| G2 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| G3 | DDR_dq[10] | | PS_DDR_DQ10_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| G4 | DDR_addr[11] | | PS_DDR_A11_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| G5 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | |
+| G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| G14 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G15 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G18 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G19 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G20 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H1 | DDR_dq[14] | | PS_DDR_DQ14_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| H2 | DDR_dq[13] | | PS_DDR_DQ13_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| H3 | DDR_dq[11] | | PS_DDR_DQ11_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| H5 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | |
+| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| H15 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H16 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H17 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H18 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H20 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J1 | DDR_dq[15] | | PS_DDR_DQ15_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J3 | DDR_dq[12] | | PS_DDR_DQ12_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| J4 | DDR_addr[9] | | PS_DDR_A9_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| J5 | DDR_ba[2] | | PS_DDR_BA2_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J14 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J15 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J16 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| J18 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J20 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K1 | DDR_addr[8] | | PS_DDR_A8_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| K2 | DDR_addr[1] | | PS_DDR_A1_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| K3 | DDR_addr[3] | | PS_DDR_A3_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| K4 | DDR_addr[7] | | PS_DDR_A7_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| K9 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K14 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K16 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K17 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K18 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K19 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| L1 | DDR_addr[5] | | PS_DDR_A5_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L2 | DDR_ck_p | | PS_DDR_CKP_502 | IN | DIFF_SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| L4 | DDR_addr[6] | | PS_DDR_A6_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L5 | DDR_ba[0] | | PS_DDR_BA0_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L10 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L14 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L15 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L16 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L17 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L19 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L20 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M2 | DDR_ck_n | | PS_DDR_CKN_502 | IN | DIFF_SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M3 | DDR_addr[2] | | PS_DDR_A2_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M4 | DDR_addr[4] | | PS_DDR_A4_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M5 | DDR_we_n | | PS_DDR_WE_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
+| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M14 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M15 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | |
+| M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M19 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| M20 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N1 | DDR_cs_n | | PS_DDR_CS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N2 | DDR_addr[0] | | PS_DDR_A0_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N3 | DDR_cke | | PS_DDR_CKE_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N5 | DDR_odt | | PS_DDR_ODT_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | |
+| N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N15 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N16 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N17 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N18 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| N20 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P1 | DDR_dq[16] | | PS_DDR_DQ16_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| P3 | DDR_dq[17] | | PS_DDR_DQ17_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| P4 | DDR_ras_n | | PS_DDR_RAS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| P5 | DDR_cas_n | | PS_DDR_CAS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | | | |
+| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P15 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P16 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P19 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P20 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R1 | DDR_dq[19] | | PS_DDR_DQ19_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| R2 | DDR_dqs_p[2] | | PS_DDR_DQS_P2_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| R3 | DDR_dq[18] | | PS_DDR_DQ18_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| R4 | DDR_ba[1] | | PS_DDR_BA1_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | |
+| R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R14 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R18 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R19 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T1 | DDR_dm[2] | | PS_DDR_DM2_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| T2 | DDR_dqs_n[2] | | PS_DDR_DQS_N2_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T4 | DDR_dq[20] | | PS_DDR_DQ20_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| T5 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | |
+| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T8 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
+| T9 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T10 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T14 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T15 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T16 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T17 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| T19 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T20 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| U2 | DDR_dq[22] | | PS_DDR_DQ22_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| U3 | DDR_dq[23] | | PS_DDR_DQ23_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| U4 | DDR_dq[21] | | PS_DDR_DQ21_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| U5 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U7 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U8 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U9 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U10 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U11 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
+| U12 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U13 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U14 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U15 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U17 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U18 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U19 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U20 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V1 | DDR_dq[24] | | PS_DDR_DQ24_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| V2 | DDR_dq[30] | | PS_DDR_DQ30_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| V3 | DDR_dq[31] | | PS_DDR_DQ31_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| V5 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V6 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V7 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V8 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V10 | | High Range | IO_L21N_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V11 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V12 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V13 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V16 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V20 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W1 | DDR_dq[26] | | PS_DDR_DQ26_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W3 | DDR_dq[29] | | PS_DDR_DQ29_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| W4 | DDR_dqs_n[3] | | PS_DDR_DQS_N3_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| W5 | DDR_dqs_p[3] | | PS_DDR_DQS_P3_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| W6 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W7 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
+| W8 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W9 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W10 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W11 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W13 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W14 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W15 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W16 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| W18 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W19 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W20 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y1 | DDR_dm[3] | | PS_DDR_DM3_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| Y2 | DDR_dq[28] | | PS_DDR_DQ28_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| Y3 | DDR_dq[25] | | PS_DDR_DQ25_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| Y4 | DDR_dq[27] | | PS_DDR_DQ27_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
+| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y6 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y7 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y8 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y9 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
+| Y11 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y12 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y13 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y16 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y17 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
++------------+-------------------+------------+-------------------------+-------------+-------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.pb b/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e0f8955b965a8fae888d67ffd231ba8ecfecdc25
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..3b01834ad95078b7a4e30c6c9e486c5d10b32738
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.rpt
@@ -0,0 +1,95 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:07:20 2021
+| Host : joan running 64-bit unknown
+| Command : report_methodology -file overlay_methodology_drc_routed.rpt -pb overlay_methodology_drc_routed.pb -rpx overlay_methodology_drc_routed.rpx
+| Design : overlay
+| Device : xc7z020clg400-1
+| Speed File : -1
+| Design State : Fully Routed
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Max violations: <unlimited>
+ Violations found: 3
++---------+----------+------------------------------+------------+
+| Rule | Severity | Description | Violations |
++---------+----------+------------------------------+------------+
+| LUTAR-1 | Warning | LUT drives async reset alert | 3 |
++---------+----------+------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+LUTAR-1#1 Warning
+LUT drives async reset alert
+LUT cell axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR
+ (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
+Related violations: <none>
+
+LUTAR-1#2 Warning
+LUT drives async reset alert
+LUT cell axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR
+ (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
+Related violations: <none>
+
+LUTAR-1#3 Warning
+LUT drives async reset alert
+LUT cell axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg/PRE,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[0]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR,
+axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR
+ (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
+Related violations: <none>
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.rpx b/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..f2a422d2e0560855bb9f9dceeecab7c2a8e0df06
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.rpx differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_opt.dcp b/rtl-proj/rtl.runs/impl_1/overlay_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..1edd745af15984ecff89f920e9d3decac61431d9
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_opt.dcp differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_physopt.dcp b/rtl-proj/rtl.runs/impl_1/overlay_physopt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..5b2885da35e9c7f4b4617950f1a5b2716fab38c3
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_physopt.dcp differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_placed.dcp b/rtl-proj/rtl.runs/impl_1/overlay_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..a699be50f6ca78a422facc22debe615952d58a70
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_placed.dcp differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_power_routed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_power_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..34ea689dbc694e46aab85cfc5f0f8913a2636cbd
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_power_routed.rpt
@@ -0,0 +1,165 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:07:22 2021
+| Host : joan running 64-bit unknown
+| Command : report_power -file overlay_power_routed.rpt -pb overlay_power_summary_routed.pb -rpx overlay_power_routed.rpx
+| Design : overlay
+| Device : xc7z020clg400-1
+| Design State : routed
+| Grade : commercial
+| Process : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W) | 1.674 |
+| Design Power Budget (W) | Unspecified* |
+| Power Budget Margin (W) | NA |
+| Dynamic (W) | 1.538 |
+| Device Static (W) | 0.136 |
+| Effective TJA (C/W) | 11.5 |
+| Max Ambient (C) | 65.7 |
+| Junction Temperature (C) | 44.3 |
+| Confidence Level | Medium |
+| Setting File | --- |
+| Simulation Activity File | --- |
+| Design Nets Matched | NA |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++--------------------------+-----------+----------+-----------+-----------------+
+| On-Chip | Power (W) | Used | Available | Utilization (%) |
++--------------------------+-----------+----------+-----------+-----------------+
+| Clocks | 0.008 | 3 | --- | --- |
+| Slice Logic | 0.001 | 8474 | --- | --- |
+| LUT as Logic | <0.001 | 2762 | 53200 | 5.19 |
+| CARRY4 | <0.001 | 93 | 13300 | 0.70 |
+| Register | <0.001 | 4075 | 106400 | 3.83 |
+| LUT as Shift Register | <0.001 | 205 | 17400 | 1.18 |
+| Others | 0.000 | 442 | --- | --- |
+| LUT as Distributed RAM | 0.000 | 18 | 17400 | 0.10 |
+| Signals | 0.002 | 6175 | --- | --- |
+| Block RAM | <0.001 | 2 | 140 | 1.43 |
+| PS7 | 1.527 | 1 | --- | --- |
+| Static Power | 0.136 | | | |
+| Total | 1.674 | | | |
++--------------------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint | 1.000 | 0.025 | 0.011 | 0.015 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.015 | 0.000 | 0.015 | NA | Unspecified | NA |
+| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA |
+| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccpint | 1.000 | 0.754 | 0.724 | 0.030 | NA | Unspecified | NA |
+| Vccpaux | 1.800 | 0.060 | 0.050 | 0.010 | NA | Unspecified | NA |
+| Vccpll | 1.800 | 0.018 | 0.015 | 0.003 | NA | Unspecified | NA |
+| Vcco_ddr | 1.500 | 0.459 | 0.457 | 0.002 | NA | Unspecified | NA |
+| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data | Confidence | Details | Action |
++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High | Design is routed | |
+| Clock nodes activity | High | User specified more than 95% of clocks | |
+| I/O nodes activity | High | User specified more than 95% of inputs | |
+| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models | High | Device models are Production | |
+| | | | |
+| Overall confidence level | Medium | | |
++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+------------------------+
+| Ambient Temp (C) | 25.0 |
+| ThetaJA (C/W) | 11.5 |
+| Airflow (LFM) | 250 |
+| Heat Sink | none |
+| ThetaSA (C/W) | 0.0 |
+| Board Selection | medium (10"x10") |
+| # of Board Layers | 8to11 (8 to 11 Layers) |
+| Board Temperature (C) | 25.0 |
++-----------------------+------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++------------+--------------------------------+-----------------+
+| Clock | Domain | Constraint (ns) |
++------------+--------------------------------+-----------------+
+| clk_fpga_0 | ps/inst/FCLK_CLK_unbuffered[0] | 20.0 |
++------------+--------------------------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++-------------------------+-----------+
+| Name | Power (W) |
++-------------------------+-----------+
+| overlay | 1.538 |
+| axi_dma_0 | 0.005 |
+| U0 | 0.005 |
+| I_PRMRY_DATAMOVER | 0.004 |
+| axi_mem_intercon | 0.002 |
+| ps | 1.528 |
+| inst | 1.528 |
+| ps_axi_periph | 0.002 |
+| s00_couplers | 0.002 |
+| auto_pc | 0.002 |
++-------------------------+-----------+
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_power_routed.rpx b/rtl-proj/rtl.runs/impl_1/overlay_power_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..ace68e78ec8627369c68439050c78c82429e34a1
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_power_routed.rpx differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_power_summary_routed.pb b/rtl-proj/rtl.runs/impl_1/overlay_power_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..1f733b234220540e13e88f07602ebabc443c9f55
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_power_summary_routed.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_route_status.pb b/rtl-proj/rtl.runs/impl_1/overlay_route_status.pb
new file mode 100644
index 0000000000000000000000000000000000000000..968af17cbe60a057f4628edb37dcd91ac562042b
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_route_status.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_route_status.rpt b/rtl-proj/rtl.runs/impl_1/overlay_route_status.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..e32f2482b73755f375a24c18e8331583ac135b87
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_route_status.rpt
@@ -0,0 +1,12 @@
+Design Route Status
+ : # nets :
+ ------------------------------------------- : ----------- :
+ # of logical nets.......................... : 10140 :
+ # of nets not needing routing.......... : 3831 :
+ # of internally routed nets........ : 3784 :
+ # of nets with no loads............ : 47 :
+ # of routable nets..................... : 6309 :
+ # of fully routed nets............. : 6309 :
+ # of nets with routing errors.......... : 0 :
+ ------------------------------------------- : ----------- :
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_routed.dcp b/rtl-proj/rtl.runs/impl_1/overlay_routed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..7683428dd7e18ae6f13c664d27c87f44b8e53819
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_routed.dcp differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.pb b/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..7c93349eaa3bdb78a48ca0560d556f22ed8f9485
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..0521af5c7e35a3e8d7e6ee5193efe98287775cf8
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.rpt
@@ -0,0 +1,2525 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:07:23 2021
+| Host : joan running 64-bit unknown
+| Command : report_timing_summary -max_paths 10 -file overlay_timing_summary_routed.rpt -pb overlay_timing_summary_routed.pb -rpx overlay_timing_summary_routed.rpx -warn_on_violation
+| Design : overlay
+| Device : 7z020-clg400
+| Speed File : -1 PRODUCTION 1.12 2019-11-22
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+ Enable Multi Corner Analysis : Yes
+ Enable Pessimism Removal : Yes
+ Pessimism Removal Resolution : Nearest Common Node
+ Enable Input Delay Default Clock : No
+ Enable Preset / Clear Arcs : No
+ Disable Flight Delays : No
+ Ignore I/O Paths : No
+ Timing Early Launch at Borrowing Latches : No
+ Borrow Time for Max Delay Exceptions : Yes
+ Merge Timing Exceptions : Yes
+
+ Corner Analyze Analyze
+ Name Max Paths Min Paths
+ ------ --------- ---------
+ Slow Yes Yes
+ Fast Yes Yes
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (0)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (0)
+5. checking no_input_delay (0)
+6. checking no_output_delay (0)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (0)
+------------------------
+ There are 0 register/latch pins with no clock.
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (0)
+------------------------------------------------
+ There are 0 pins that are not constrained for maximum delay.
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (0)
+------------------------------
+ There are 0 input ports with no input delay specified.
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (0)
+-------------------------------
+ There are 0 ports with no output delay specified.
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+ 9.582 0.000 0 10974 0.030 0.000 0 10974 8.750 0.000 0 4399
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock Waveform(ns) Period(ns) Frequency(MHz)
+----- ------------ ---------- --------------
+clk_fpga_0 {0.000 10.000} 20.000 50.000
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+clk_fpga_0 9.582 0.000 0 10878 0.030 0.000 0 10878 8.750 0.000 0 4399
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+**async_default** clk_fpga_0 clk_fpga_0 16.476 0.000 0 96 0.483 0.000 0 96
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_fpga_0
+ To Clock: clk_fpga_0
+
+Setup : 0 Failing Endpoints, Worst Slack 9.582ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.030ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 9.582ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[19]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.943ns (logic 3.234ns (32.526%) route 6.709ns (67.474%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.081ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.739ns = ( 22.740 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.622 11.989 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X25Y24 LUT6 (Prop_lut6_I2_O) 0.310 12.299 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[19]_i_1/O
+ net (fo=2, routed) 0.579 12.878 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[19]
+ SLICE_X27Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.560 22.740 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X27Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[19]/C
+ clock pessimism 0.115 22.854
+ clock uncertainty -0.302 22.552
+ SLICE_X27Y21 FDRE (Setup_fdre_C_D) -0.093 22.459 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[19]
+ -------------------------------------------------------------------
+ required time 22.459
+ arrival time -12.878
+ -------------------------------------------------------------------
+ slack 9.582
+
+Slack (MET) : 9.675ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[18]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.861ns (logic 3.234ns (32.795%) route 6.627ns (67.205%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.081ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.739ns = ( 22.740 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.467 11.834 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X26Y25 LUT6 (Prop_lut6_I2_O) 0.310 12.144 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[18]_i_1/O
+ net (fo=2, routed) 0.652 12.796 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[18]
+ SLICE_X27Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[18]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.560 22.740 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X27Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[18]/C
+ clock pessimism 0.115 22.854
+ clock uncertainty -0.302 22.552
+ SLICE_X27Y21 FDRE (Setup_fdre_C_D) -0.081 22.471 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[18]
+ -------------------------------------------------------------------
+ required time 22.471
+ arrival time -12.796
+ -------------------------------------------------------------------
+ slack 9.675
+
+Slack (MET) : 9.681ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[17]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.870ns (logic 3.234ns (32.767%) route 6.636ns (67.233%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.081ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.739ns = ( 22.740 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.475 11.842 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X26Y25 LUT6 (Prop_lut6_I2_O) 0.310 12.152 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[17]_i_1/O
+ net (fo=2, routed) 0.653 12.805 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[17]
+ SLICE_X27Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[17]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.560 22.740 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X27Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[17]/C
+ clock pessimism 0.115 22.854
+ clock uncertainty -0.302 22.552
+ SLICE_X27Y21 FDRE (Setup_fdre_C_D) -0.067 22.485 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[17]
+ -------------------------------------------------------------------
+ required time 22.485
+ arrival time -12.805
+ -------------------------------------------------------------------
+ slack 9.681
+
+Slack (MET) : 9.729ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[19]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.857ns (logic 3.234ns (32.809%) route 6.623ns (67.191%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.081ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.739ns = ( 22.740 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.622 11.989 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X25Y24 LUT6 (Prop_lut6_I2_O) 0.310 12.299 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[19]_i_1/O
+ net (fo=2, routed) 0.493 12.792 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[19]
+ SLICE_X26Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[19]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.560 22.740 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X26Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[19]/C
+ clock pessimism 0.115 22.854
+ clock uncertainty -0.302 22.552
+ SLICE_X26Y21 FDRE (Setup_fdre_C_D) -0.031 22.521 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[19]
+ -------------------------------------------------------------------
+ required time 22.521
+ arrival time -12.792
+ -------------------------------------------------------------------
+ slack 9.729
+
+Slack (MET) : 9.805ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[20]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.769ns (logic 3.234ns (33.104%) route 6.535ns (66.896%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.081ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.739ns = ( 22.740 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.412 11.779 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X25Y24 LUT6 (Prop_lut6_I2_O) 0.310 12.089 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[20]_i_1/O
+ net (fo=2, routed) 0.616 12.704 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[20]
+ SLICE_X27Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[20]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.560 22.740 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X27Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[20]/C
+ clock pessimism 0.115 22.854
+ clock uncertainty -0.302 22.552
+ SLICE_X27Y21 FDRE (Setup_fdre_C_D) -0.043 22.509 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[20]
+ -------------------------------------------------------------------
+ required time 22.509
+ arrival time -12.704
+ -------------------------------------------------------------------
+ slack 9.805
+
+Slack (MET) : 9.813ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[18]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.721ns (logic 3.234ns (33.267%) route 6.487ns (66.733%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.083ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.737ns = ( 22.737 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.467 11.834 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X26Y25 LUT6 (Prop_lut6_I2_O) 0.310 12.144 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[18]_i_1/O
+ net (fo=2, routed) 0.512 12.656 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[18]
+ SLICE_X27Y22 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[18]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.558 22.737 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X27Y22 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[18]/C
+ clock pessimism 0.115 22.852
+ clock uncertainty -0.302 22.550
+ SLICE_X27Y22 FDRE (Setup_fdre_C_D) -0.081 22.469 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[18]
+ -------------------------------------------------------------------
+ required time 22.469
+ arrival time -12.656
+ -------------------------------------------------------------------
+ slack 9.813
+
+Slack (MET) : 9.819ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[17]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.730ns (logic 3.234ns (33.238%) route 6.496ns (66.762%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.083ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.737ns = ( 22.737 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.475 11.842 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X26Y25 LUT6 (Prop_lut6_I2_O) 0.310 12.152 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[17]_i_1/O
+ net (fo=2, routed) 0.513 12.665 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[17]
+ SLICE_X27Y22 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[17]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.558 22.737 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X27Y22 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[17]/C
+ clock pessimism 0.115 22.852
+ clock uncertainty -0.302 22.550
+ SLICE_X27Y22 FDRE (Setup_fdre_C_D) -0.067 22.483 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[17]
+ -------------------------------------------------------------------
+ required time 22.483
+ arrival time -12.665
+ -------------------------------------------------------------------
+ slack 9.819
+
+Slack (MET) : 9.820ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[20]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.769ns (logic 3.234ns (33.104%) route 6.535ns (66.896%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.081ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.739ns = ( 22.740 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.412 11.779 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X25Y24 LUT6 (Prop_lut6_I2_O) 0.310 12.089 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[20]_i_1/O
+ net (fo=2, routed) 0.616 12.704 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[20]
+ SLICE_X26Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[20]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.560 22.740 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X26Y21 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[20]/C
+ clock pessimism 0.115 22.854
+ clock uncertainty -0.302 22.552
+ SLICE_X26Y21 FDRE (Setup_fdre_C_D) -0.028 22.524 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[20]
+ -------------------------------------------------------------------
+ required time 22.524
+ arrival time -12.704
+ -------------------------------------------------------------------
+ slack 9.820
+
+Slack (MET) : 9.841ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.655ns (logic 3.234ns (33.496%) route 6.421ns (66.504%))
+ Logic Levels: 10 (CARRY4=8 LUT4=1 LUT6=1)
+ Clock Path Skew: -0.156ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.664ns = ( 22.664 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 f pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 3.955 11.322 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X26Y27 LUT4 (Prop_lut4_I3_O) 0.310 11.632 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[0]_i_1/O
+ net (fo=2, routed) 0.957 12.590 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[0]
+ SLICE_X34Y30 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.485 22.664 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X34Y30 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[0]/C
+ clock pessimism 0.115 22.779
+ clock uncertainty -0.302 22.477
+ SLICE_X34Y30 FDRE (Setup_fdre_C_D) -0.047 22.430 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[0]
+ -------------------------------------------------------------------
+ required time 22.430
+ arrival time -12.590
+ -------------------------------------------------------------------
+ slack 9.841
+
+Slack (MET) : 9.849ns (required time - arrival time)
+ Source: pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[21]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 9.695ns (logic 3.234ns (33.357%) route 6.461ns (66.643%))
+ Logic Levels: 10 (CARRY4=8 LUT6=2)
+ Clock Path Skew: -0.087ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.733ns = ( 22.733 - 20.000 )
+ Source Clock Delay (SCD): 2.935ns
+ Clock Pessimism Removal (CPR): 0.115ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.641 2.935 pixel/inst/control_s_axi_U/ap_clk
+ SLICE_X34Y81 FDRE r pixel/inst/control_s_axi_U/int_len_i_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y81 FDRE (Prop_fdre_C_Q) 0.478 3.413 r pixel/inst/control_s_axi_U/int_len_i_reg[1]/Q
+ net (fo=3, routed) 0.671 4.084 pixel/inst/control_s_axi_U/len_i[1]
+ SLICE_X35Y81 CARRY4 (Prop_carry4_S[0]_CO[3])
+ 0.827 4.911 r pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1/CO[3]
+ net (fo=1, routed) 0.000 4.911 pixel/inst/control_s_axi_U/int_len_o_reg[4]_i_1_n_0
+ SLICE_X35Y82 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.025 r pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.025 pixel/inst/control_s_axi_U/int_len_o_reg[8]_i_1_n_0
+ SLICE_X35Y83 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.139 r pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.139 pixel/inst/control_s_axi_U/int_len_o_reg[12]_i_1_n_0
+ SLICE_X35Y84 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.253 r pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.253 pixel/inst/control_s_axi_U/int_len_o_reg[16]_i_1_n_0
+ SLICE_X35Y85 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.114 5.367 r pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1/CO[3]
+ net (fo=1, routed) 0.000 5.367 pixel/inst/control_s_axi_U/int_len_o_reg[20]_i_1_n_0
+ SLICE_X35Y86 CARRY4 (Prop_carry4_CI_O[2])
+ 0.256 5.623 r pixel/inst/control_s_axi_U/int_len_o_reg[24]_i_1/O[2]
+ net (fo=2, routed) 0.837 6.460 pixel/inst/control_s_axi_U/add_ln691_fu_122_p2[23]
+ SLICE_X34Y84 LUT6 (Prop_lut6_I3_O) 0.302 6.762 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9/O
+ net (fo=1, routed) 0.000 6.762 pixel/inst/control_s_axi_U/B_V_data_1_payload_A[31]_i_9_n_0
+ SLICE_X34Y84 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 7.138 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4/CO[3]
+ net (fo=1, routed) 0.000 7.138 pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_4_n_0
+ SLICE_X34Y85 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.229 7.367 r pixel/inst/control_s_axi_U/B_V_data_1_payload_A_reg[31]_i_3/CO[2]
+ net (fo=32, routed) 4.387 11.754 pixel/inst/regslice_both_din_V_data_V_U/CO[0]
+ SLICE_X25Y24 LUT6 (Prop_lut6_I2_O) 0.310 12.064 r pixel/inst/regslice_both_din_V_data_V_U/B_V_data_1_payload_A[21]_i_1/O
+ net (fo=2, routed) 0.566 12.630 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_A_reg[31]_0[21]
+ SLICE_X28Y24 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[21]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.554 22.733 pixel/inst/regslice_both_dout_V_data_V_U/ap_clk
+ SLICE_X28Y24 FDRE r pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[21]/C
+ clock pessimism 0.115 22.848
+ clock uncertainty -0.302 22.546
+ SLICE_X28Y24 FDRE (Setup_fdre_C_D) -0.067 22.479 pixel/inst/regslice_both_dout_V_data_V_U/B_V_data_1_payload_B_reg[21]
+ -------------------------------------------------------------------
+ required time 22.479
+ arrival time -12.630
+ -------------------------------------------------------------------
+ slack 9.849
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.030ns (arrival time - required time)
+ Source: axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_arbiter.m_mesg_i_reg[6]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_AADDR_Q_reg[5]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.300ns (logic 0.128ns (42.634%) route 0.172ns (57.366%))
+ Logic Levels: 0
+ Clock Path Skew: 0.254ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.211ns
+ Source Clock Delay (SCD): 0.927ns
+ Clock Pessimism Removal (CPR): 0.030ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.591 0.927 axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/aclk
+ SLICE_X31Y49 FDRE r axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_arbiter.m_mesg_i_reg[6]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X31Y49 FDRE (Prop_fdre_C_Q) 0.128 1.055 r axi_mem_intercon/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/gen_arbiter.m_mesg_i_reg[6]/Q
+ net (fo=1, routed) 0.172 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/s_axi_awaddr[5]
+ SLICE_X28Y50 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_AADDR_Q_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.845 1.211 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/aclk
+ SLICE_X28Y50 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_AADDR_Q_reg[5]/C
+ clock pessimism -0.030 1.181
+ SLICE_X28Y50 FDRE (Hold_fdre_C_D) 0.016 1.197 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_AADDR_Q_reg[5]
+ -------------------------------------------------------------------
+ required time -1.197
+ arrival time 1.227
+ -------------------------------------------------------------------
+ slack 0.030
+
+Slack (MET) : 0.037ns (arrival time - required time)
+ Source: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[16]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4/D
+ (rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.254ns (logic 0.141ns (55.522%) route 0.113ns (44.478%))
+ Logic Levels: 0
+ Clock Path Skew: 0.034ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.191ns
+ Source Clock Delay (SCD): 0.893ns
+ Clock Pessimism Removal (CPR): 0.264ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.557 0.893 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
+ SLICE_X33Y57 FDRE r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[16]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X33Y57 FDRE (Prop_fdre_C_Q) 0.141 1.034 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[16]/Q
+ net (fo=1, routed) 0.113 1.147 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[16]
+ SLICE_X34Y56 SRL16E r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.825 1.191 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk
+ SLICE_X34Y56 SRL16E r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4/CLK
+ clock pessimism -0.264 0.927
+ SLICE_X34Y56 SRL16E (Hold_srl16e_CLK_D)
+ 0.183 1.110 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][38]_srl4
+ -------------------------------------------------------------------
+ required time -1.110
+ arrival time 1.147
+ -------------------------------------------------------------------
+ slack 0.037
+
+Slack (MET) : 0.043ns (arrival time - required time)
+ Source: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[8]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DIADI[8]
+ (rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.418ns (logic 0.164ns (39.251%) route 0.254ns (60.749%))
+ Logic Levels: 0
+ Clock Path Skew: 0.078ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.229ns
+ Source Clock Delay (SCD): 0.888ns
+ Clock Pessimism Removal (CPR): 0.263ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.552 0.888 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/m_axi_s2mm_aclk
+ SLICE_X36Y28 FDRE r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[8]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X36Y28 FDRE (Prop_fdre_C_Q) 0.164 1.052 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[8]/Q
+ net (fo=1, routed) 0.254 1.305 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[8]
+ RAMB36_X2Y6 RAMB36E1 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DIADI[8]
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.863 1.229 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka
+ RAMB36_X2Y6 RAMB36E1 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
+ clock pessimism -0.263 0.966
+ RAMB36_X2Y6 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIADI[8])
+ 0.296 1.262 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg
+ -------------------------------------------------------------------
+ required time -1.262
+ arrival time 1.305
+ -------------------------------------------------------------------
+ slack 0.043
+
+Slack (MET) : 0.044ns (arrival time - required time)
+ Source: ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/s_awid_r_reg[7]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4/D
+ (rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.244ns (logic 0.141ns (57.770%) route 0.103ns (42.230%))
+ Logic Levels: 0
+ Clock Path Skew: 0.017ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.297ns
+ Source Clock Delay (SCD): 0.994ns
+ Clock Pessimism Removal (CPR): 0.286ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.658 0.994 ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aclk
+ SLICE_X28Y103 FDRE r ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/s_awid_r_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X28Y103 FDRE (Prop_fdre_C_Q) 0.141 1.135 r ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/s_awid_r_reg[7]/Q
+ net (fo=1, routed) 0.103 1.238 ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/in[11]
+ SLICE_X30Y102 SRL16E r ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.931 1.297 ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/aclk
+ SLICE_X30Y102 SRL16E r ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4/CLK
+ clock pessimism -0.286 1.011
+ SLICE_X30Y102 SRL16E (Hold_srl16e_CLK_D)
+ 0.183 1.194 ps_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4
+ -------------------------------------------------------------------
+ required time -1.194
+ arrival time 1.238
+ -------------------------------------------------------------------
+ slack 0.044
+
+Slack (MET) : 0.047ns (arrival time - required time)
+ Source: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_btt_reg_reg[3]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4/D
+ (rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.369ns (logic 0.128ns (34.723%) route 0.241ns (65.277%))
+ Logic Levels: 0
+ Clock Path Skew: 0.265ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.195ns
+ Source Clock Delay (SCD): 0.895ns
+ Clock Pessimism Removal (CPR): 0.035ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.559 0.895 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
+ SLICE_X51Y47 FDRE r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_btt_reg_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X51Y47 FDRE (Prop_fdre_C_Q) 0.128 1.023 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_btt_reg_reg[3]/Q
+ net (fo=1, routed) 0.241 1.263 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[3]
+ SLICE_X46Y45 SRL16E r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.829 1.195 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk
+ SLICE_X46Y45 SRL16E r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4/CLK
+ clock pessimism -0.035 1.160
+ SLICE_X46Y45 SRL16E (Hold_srl16e_CLK_D)
+ 0.056 1.216 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][27]_srl4
+ -------------------------------------------------------------------
+ required time -1.216
+ arrival time 1.263
+ -------------------------------------------------------------------
+ slack 0.047
+
+Slack (MET) : 0.048ns (arrival time - required time)
+ Source: axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_i_reg[23]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[23]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.324ns (logic 0.128ns (39.516%) route 0.196ns (60.484%))
+ Logic Levels: 0
+ Clock Path Skew: 0.259ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.184ns
+ Source Clock Delay (SCD): 0.890ns
+ Clock Pessimism Removal (CPR): 0.035ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.554 0.890 axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/s_axi_lite_aclk
+ SLICE_X44Y61 FDRE r axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_i_reg[23]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X44Y61 FDRE (Prop_fdre_C_Q) 0.128 1.018 r axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_i_reg[23]/Q
+ net (fo=2, routed) 0.196 1.214 axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[25]_0[23]
+ SLICE_X52Y61 FDRE r axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[23]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.818 1.184 axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/s_axi_lite_aclk
+ SLICE_X52Y61 FDRE r axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[23]/C
+ clock pessimism -0.035 1.149
+ SLICE_X52Y61 FDRE (Hold_fdre_C_D) 0.017 1.166 axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_S2MM_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[23]
+ -------------------------------------------------------------------
+ required time -1.166
+ arrival time 1.214
+ -------------------------------------------------------------------
+ slack 0.048
+
+Slack (MET) : 0.048ns (arrival time - required time)
+ Source: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[21]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DIADI[21]
+ (rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.421ns (logic 0.164ns (38.971%) route 0.257ns (61.029%))
+ Logic Levels: 0
+ Clock Path Skew: 0.076ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.229ns
+ Source Clock Delay (SCD): 0.890ns
+ Clock Pessimism Removal (CPR): 0.263ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.554 0.890 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/m_axi_s2mm_aclk
+ SLICE_X34Y28 FDRE r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[21]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X34Y28 FDRE (Prop_fdre_C_Q) 0.164 1.054 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[21]/Q
+ net (fo=1, routed) 0.257 1.310 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[21]
+ RAMB36_X2Y6 RAMB36E1 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DIADI[21]
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.863 1.229 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka
+ RAMB36_X2Y6 RAMB36E1 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
+ clock pessimism -0.263 0.966
+ RAMB36_X2Y6 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIADI[21])
+ 0.296 1.262 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg
+ -------------------------------------------------------------------
+ required time -1.262
+ arrival time 1.310
+ -------------------------------------------------------------------
+ slack 0.048
+
+Slack (MET) : 0.050ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[1]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.470ns (logic 0.252ns (53.561%) route 0.218ns (46.439%))
+ Logic Levels: 2 (CARRY4=1 LUT6=1)
+ Clock Path Skew: 0.286ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.226ns
+ Source Clock Delay (SCD): 0.910ns
+ Clock Pessimism Removal (CPR): 0.030ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.574 0.910 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/aclk
+ SLICE_X27Y50 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X27Y50 FDRE (Prop_fdre_C_Q) 0.141 1.051 r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[1]/Q
+ net (fo=2, routed) 0.218 1.269 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q[1]
+ SLICE_X26Y49 LUT6 (Prop_lut6_I2_O) 0.045 1.314 r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr[3]_i_4/O
+ net (fo=1, routed) 0.000 1.314 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr[3]_i_4_n_0
+ SLICE_X26Y49 CARRY4 (Prop_carry4_S[1]_O[1])
+ 0.066 1.380 r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[3]_i_1/O[1]
+ net (fo=1, routed) 0.000 1.380 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/p_0_in[1]
+ SLICE_X26Y49 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.860 1.226 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/aclk
+ SLICE_X26Y49 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[1]/C
+ clock pessimism -0.030 1.196
+ SLICE_X26Y49 FDRE (Hold_fdre_C_D) 0.134 1.330 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[1]
+ -------------------------------------------------------------------
+ required time -1.330
+ arrival time 1.380
+ -------------------------------------------------------------------
+ slack 0.050
+
+Slack (MET) : 0.052ns (arrival time - required time)
+ Source: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[9]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DIADI[9]
+ (rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.425ns (logic 0.141ns (33.183%) route 0.284ns (66.817%))
+ Logic Levels: 0
+ Clock Path Skew: 0.076ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.229ns
+ Source Clock Delay (SCD): 0.890ns
+ Clock Pessimism Removal (CPR): 0.263ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.554 0.890 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/m_axi_s2mm_aclk
+ SLICE_X37Y30 FDRE r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[9]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X37Y30 FDRE (Prop_fdre_C_Q) 0.141 1.031 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_reg[9]/Q
+ net (fo=1, routed) 0.284 1.314 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/dina[9]
+ RAMB36_X2Y6 RAMB36E1 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/DIADI[9]
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.863 1.229 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka
+ RAMB36_X2Y6 RAMB36E1 r axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
+ clock pessimism -0.263 0.966
+ RAMB36_X2Y6 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIADI[9])
+ 0.296 1.262 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg
+ -------------------------------------------------------------------
+ required time -1.262
+ arrival time 1.314
+ -------------------------------------------------------------------
+ slack 0.052
+
+Slack (MET) : 0.054ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[3]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: clk_fpga_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.440ns (logic 0.348ns (79.109%) route 0.092ns (20.891%))
+ Logic Levels: 3 (CARRY4=2 LUT6=1)
+ Clock Path Skew: 0.252ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.210ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.030ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/aclk
+ SLICE_X27Y49 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X27Y49 FDRE (Prop_fdre_C_Q) 0.141 1.069 r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[3]/Q
+ net (fo=2, routed) 0.091 1.160 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q[3]
+ SLICE_X26Y49 LUT6 (Prop_lut6_I2_O) 0.045 1.205 r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr[3]_i_2/O
+ net (fo=1, routed) 0.000 1.205 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr[3]_i_2_n_0
+ SLICE_X26Y49 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.109 1.314 r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[3]_i_1/CO[3]
+ net (fo=1, routed) 0.001 1.314 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[3]_i_1_n_0
+ SLICE_X26Y50 CARRY4 (Prop_carry4_CI_O[0])
+ 0.053 1.367 r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[7]_i_1/O[0]
+ net (fo=1, routed) 0.000 1.367 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/p_0_in[4]
+ SLICE_X26Y50 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.844 1.210 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/aclk
+ SLICE_X26Y50 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[4]/C
+ clock pessimism -0.030 1.180
+ SLICE_X26Y50 FDRE (Hold_fdre_C_D) 0.134 1.314 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/next_mi_addr_reg[4]
+ -------------------------------------------------------------------
+ required time -1.314
+ arrival time 1.367
+ -------------------------------------------------------------------
+ slack 0.054
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_fpga_0
+Waveform(ns): { 0.000 10.000 }
+Period(ns): 20.000
+Sources: { ps/inst/PS7_i/FCLKCLK[0] }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y6 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK
+Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X1Y6 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
+Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X2Y6 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK
+Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X2Y6 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK
+Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/I
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X39Y54 axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_MM2S_SMPL_SM/FSM_sequential_smpl_cs_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X39Y54 axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_MM2S_SMPL_SM/FSM_sequential_smpl_cs_reg[1]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X38Y56 axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_MM2S_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[0]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X37Y61 axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_MM2S_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[10]/C
+Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X38Y56 axi_dma_0/U0/INCLUDE_MM2S_SOF_EOF_GENERATOR.I_MM2S_DMA_MNGR/GEN_MM2S_DMA_CONTROL.GEN_SIMPLE_DMA_MODE.I_MM2S_SMPL_SM/GEN_CMD_BTT_EQL_23.cmnd_data_reg[11]/C
+Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMA/CLK
+Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMA/CLK
+Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMA_D1/CLK
+Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMA_D1/CLK
+Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMB/CLK
+Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMB/CLK
+Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMB_D1/CLK
+Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMB_D1/CLK
+Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMC/CLK
+Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMC/CLK
+High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X38Y39 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_6_8/RAMA/CLK
+High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X38Y39 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_6_8/RAMA_D1/CLK
+High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X38Y39 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_6_8/RAMB/CLK
+High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X38Y39 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_6_8/RAMB_D1/CLK
+High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X38Y39 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_6_8/RAMC/CLK
+High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X38Y39 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_6_8/RAMC_D1/CLK
+High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X38Y39 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_6_8/RAMD/CLK
+High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X38Y39 axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_6_8/RAMD_D1/CLK
+High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMA/CLK
+High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y35 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_4/RAMA_D1/CLK
+
+
+
+---------------------------------------------------------------------------------------------------
+Path Group: **async_default**
+From Clock: clk_fpga_0
+ To Clock: clk_fpga_0
+
+Setup : 0 Failing Endpoints, Worst Slack 16.476ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.483ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 16.476ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.803ns (logic 0.580ns (20.695%) route 2.223ns (79.305%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.058ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.755ns = ( 22.756 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 1.007 5.846 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X16Y37 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.576 22.756 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X16Y37 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/C
+ clock pessimism 0.230 22.985
+ clock uncertainty -0.302 22.683
+ SLICE_X16Y37 FDPE (Recov_fdpe_C_PRE) -0.361 22.322 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg
+ -------------------------------------------------------------------
+ required time 22.322
+ arrival time -5.846
+ -------------------------------------------------------------------
+ slack 16.476
+
+Slack (MET) : 16.518ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.803ns (logic 0.580ns (20.695%) route 2.223ns (79.305%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.058ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.755ns = ( 22.756 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 1.007 5.846 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X16Y37 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.576 22.756 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X16Y37 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C
+ clock pessimism 0.230 22.985
+ clock uncertainty -0.302 22.683
+ SLICE_X16Y37 FDPE (Recov_fdpe_C_PRE) -0.319 22.364 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg
+ -------------------------------------------------------------------
+ required time 22.364
+ arrival time -5.846
+ -------------------------------------------------------------------
+ slack 16.518
+
+Slack (MET) : 16.518ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.803ns (logic 0.580ns (20.695%) route 2.223ns (79.305%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.058ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.755ns = ( 22.756 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 1.007 5.846 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X16Y37 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.576 22.756 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X16Y37 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/C
+ clock pessimism 0.230 22.985
+ clock uncertainty -0.302 22.683
+ SLICE_X16Y37 FDCE (Recov_fdce_C_CLR) -0.319 22.364 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg
+ -------------------------------------------------------------------
+ required time 22.364
+ arrival time -5.846
+ -------------------------------------------------------------------
+ slack 16.518
+
+Slack (MET) : 16.518ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/CLR
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.803ns (logic 0.580ns (20.695%) route 2.223ns (79.305%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.058ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.755ns = ( 22.756 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 1.007 5.846 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg_0
+ SLICE_X16Y37 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.576 22.756 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/clk
+ SLICE_X16Y37 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/C
+ clock pessimism 0.230 22.985
+ clock uncertainty -0.302 22.683
+ SLICE_X16Y37 FDCE (Recov_fdce_C_CLR) -0.319 22.364 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg
+ -------------------------------------------------------------------
+ required time 22.364
+ arrival time -5.846
+ -------------------------------------------------------------------
+ slack 16.518
+
+Slack (MET) : 16.606ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.672ns (logic 0.580ns (21.704%) route 2.092ns (78.296%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.059ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.754ns = ( 22.754 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 0.877 5.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X16Y36 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.575 22.754 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X16Y36 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C
+ clock pessimism 0.230 22.984
+ clock uncertainty -0.302 22.682
+ SLICE_X16Y36 FDPE (Recov_fdpe_C_PRE) -0.361 22.321 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg
+ -------------------------------------------------------------------
+ required time 22.321
+ arrival time -5.715
+ -------------------------------------------------------------------
+ slack 16.606
+
+Slack (MET) : 16.606ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.672ns (logic 0.580ns (21.704%) route 2.092ns (78.296%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.059ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.754ns = ( 22.754 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 0.877 5.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X16Y36 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.575 22.754 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X16Y36 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C
+ clock pessimism 0.230 22.984
+ clock uncertainty -0.302 22.682
+ SLICE_X16Y36 FDCE (Recov_fdce_C_CLR) -0.361 22.321 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]
+ -------------------------------------------------------------------
+ required time 22.321
+ arrival time -5.715
+ -------------------------------------------------------------------
+ slack 16.606
+
+Slack (MET) : 16.608ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.672ns (logic 0.580ns (21.704%) route 2.092ns (78.296%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.059ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.754ns = ( 22.754 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 0.877 5.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X17Y36 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.575 22.754 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X17Y36 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C
+ clock pessimism 0.230 22.984
+ clock uncertainty -0.302 22.682
+ SLICE_X17Y36 FDPE (Recov_fdpe_C_PRE) -0.359 22.323 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg
+ -------------------------------------------------------------------
+ required time 22.323
+ arrival time -5.715
+ -------------------------------------------------------------------
+ slack 16.608
+
+Slack (MET) : 16.648ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.672ns (logic 0.580ns (21.704%) route 2.092ns (78.296%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.059ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.754ns = ( 22.754 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 0.877 5.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X16Y36 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.575 22.754 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X16Y36 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/C
+ clock pessimism 0.230 22.984
+ clock uncertainty -0.302 22.682
+ SLICE_X16Y36 FDPE (Recov_fdpe_C_PRE) -0.319 22.363 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg
+ -------------------------------------------------------------------
+ required time 22.363
+ arrival time -5.715
+ -------------------------------------------------------------------
+ slack 16.648
+
+Slack (MET) : 16.648ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.672ns (logic 0.580ns (21.704%) route 2.092ns (78.296%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.059ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.754ns = ( 22.754 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X15Y33 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X15Y33 FDRE (Prop_fdre_C_Q) 0.456 3.499 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
+ net (fo=2, routed) 1.216 4.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0]
+ SLICE_X16Y33 LUT3 (Prop_lut3_I1_O) 0.124 4.839 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=33, routed) 0.877 5.715 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X16Y36 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.575 22.754 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X16Y36 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C
+ clock pessimism 0.230 22.984
+ clock uncertainty -0.302 22.682
+ SLICE_X16Y36 FDCE (Recov_fdce_C_CLR) -0.319 22.363 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]
+ -------------------------------------------------------------------
+ required time 22.363
+ arrival time -5.715
+ -------------------------------------------------------------------
+ slack 16.648
+
+Slack (MET) : 16.736ns (required time - arrival time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C
+ (rising edge-triggered cell FDPE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
+ (recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Recovery (Max at Slow Process Corner)
+ Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 2.498ns (logic 0.718ns (28.744%) route 1.780ns (71.256%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: -0.059ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): 2.754ns = ( 22.754 - 20.000 )
+ Source Clock Delay (SCD): 3.043ns
+ Clock Pessimism Removal (CPR): 0.230ns
+ Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Total Input Jitter (TIJ): 0.600ns
+ Discrete Jitter (DJ): 0.000ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.193 1.193 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 1.294 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.749 3.043 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
+ SLICE_X23Y37 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X23Y37 FDPE (Prop_fdpe_C_Q) 0.419 3.462 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q
+ net (fo=3, routed) 0.857 4.319 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_wr_reg2
+ SLICE_X20Y36 LUT3 (Prop_lut3_I2_O) 0.299 4.618 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.923 5.541 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X19Y35 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 20.000 20.000 r
+ PS7_X0Y0 PS7 0.000 20.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 1.088 21.088 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 21.179 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 1.575 22.754 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X19Y35 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/C
+ clock pessimism 0.230 22.984
+ clock uncertainty -0.302 22.682
+ SLICE_X19Y35 FDCE (Recov_fdce_C_CLR) -0.405 22.277 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg
+ -------------------------------------------------------------------
+ required time 22.277
+ arrival time -5.541
+ -------------------------------------------------------------------
+ slack 16.736
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.483ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X12Y37 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X12Y37 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/C
+ clock pessimism -0.283 0.944
+ SLICE_X12Y37 FDCE (Remov_fdce_C_CLR) -0.067 0.877 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg
+ -------------------------------------------------------------------
+ required time -0.877
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.483
+
+Slack (MET) : 0.483ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/CLR
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/AR[0]
+ SLICE_X12Y37 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/clk
+ SLICE_X12Y37 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg/C
+ clock pessimism -0.283 0.944
+ SLICE_X12Y37 FDCE (Remov_fdce_C_CLR) -0.067 0.877 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_reg
+ -------------------------------------------------------------------
+ required time -0.877
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.483
+
+Slack (MET) : 0.483ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/CLR
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/AR[0]
+ SLICE_X12Y37 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/clk
+ SLICE_X12Y37 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg/C
+ clock pessimism -0.283 0.944
+ SLICE_X12Y37 FDCE (Remov_fdce_C_CLR) -0.067 0.877 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_reg
+ -------------------------------------------------------------------
+ required time -0.877
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.483
+
+Slack (MET) : 0.487ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X12Y37 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X12Y37 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C
+ clock pessimism -0.283 0.944
+ SLICE_X12Y37 FDPE (Remov_fdpe_C_PRE) -0.071 0.873 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg
+ -------------------------------------------------------------------
+ required time -0.873
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.487
+
+Slack (MET) : 0.487ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X12Y37 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X12Y37 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C
+ clock pessimism -0.283 0.944
+ SLICE_X12Y37 FDPE (Remov_fdpe_C_PRE) -0.071 0.873 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg
+ -------------------------------------------------------------------
+ required time -0.873
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.487
+
+Slack (MET) : 0.508ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X13Y37 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X13Y37 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C
+ clock pessimism -0.283 0.944
+ SLICE_X13Y37 FDCE (Remov_fdce_C_CLR) -0.092 0.852 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]
+ -------------------------------------------------------------------
+ required time -0.852
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.508
+
+Slack (MET) : 0.508ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X13Y37 FDCE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X13Y37 FDCE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C
+ clock pessimism -0.283 0.944
+ SLICE_X13Y37 FDCE (Remov_fdce_C_CLR) -0.092 0.852 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]
+ -------------------------------------------------------------------
+ required time -0.852
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.508
+
+Slack (MET) : 0.511ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X13Y37 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X13Y37 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C
+ clock pessimism -0.283 0.944
+ SLICE_X13Y37 FDPE (Remov_fdpe_C_PRE) -0.095 0.849 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg
+ -------------------------------------------------------------------
+ required time -0.849
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.511
+
+Slack (MET) : 0.511ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
+ SLICE_X13Y37 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
+ SLICE_X13Y37 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/C
+ clock pessimism -0.283 0.944
+ SLICE_X13Y37 FDPE (Remov_fdpe_C_PRE) -0.095 0.849 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg
+ -------------------------------------------------------------------
+ required time -0.849
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.511
+
+Slack (MET) : 0.511ns (arrival time - required time)
+ Source: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Destination: axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/PRE
+ (removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns})
+ Path Group: **async_default**
+ Path Type: Removal (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
+ Data Path Delay: 0.432ns (logic 0.186ns (43.104%) route 0.246ns (56.896%))
+ Logic Levels: 1 (LUT3=1)
+ Clock Path Skew: 0.016ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): 1.227ns
+ Source Clock Delay (SCD): 0.928ns
+ Clock Pessimism Removal (CPR): 0.283ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.310 0.310 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.592 0.928 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
+ SLICE_X13Y36 FDRE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X13Y36 FDRE (Prop_fdre_C_Q) 0.141 1.069 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
+ net (fo=2, routed) 0.117 1.185 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[1]
+ SLICE_X13Y37 LUT3 (Prop_lut3_I0_O) 0.045 1.230 f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
+ net (fo=32, routed) 0.129 1.359 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_reg_1
+ SLICE_X13Y37 FDPE f axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/PRE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_fpga_0 rise edge)
+ 0.000 0.000 r
+ PS7_X0Y0 PS7 0.000 0.000 r ps/inst/PS7_i/FCLKCLK[0]
+ net (fo=1, routed) 0.337 0.337 ps/inst/FCLK_CLK_unbuffered[0]
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r ps/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
+ net (fo=4400, routed) 0.861 1.227 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/clk
+ SLICE_X13Y37 FDPE r axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg/C
+ clock pessimism -0.283 0.944
+ SLICE_X13Y37 FDPE (Remov_fdpe_C_PRE) -0.095 0.849 axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_reg
+ -------------------------------------------------------------------
+ required time -0.849
+ arrival time 1.359
+ -------------------------------------------------------------------
+ slack 0.511
+
+
+
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.rpx b/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..4568b13200e7154b0cf484c25f79ea8de63a65b1
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_timing_summary_routed.rpx differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_utilization_placed.pb b/rtl-proj/rtl.runs/impl_1/overlay_utilization_placed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..80fffc5df6742a129e82fec94754331ad914954c
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/overlay_utilization_placed.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/overlay_utilization_placed.rpt b/rtl-proj/rtl.runs/impl_1/overlay_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..29fa658d097c9e75819f23ca38593ed8faf0fc58
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/overlay_utilization_placed.rpt
@@ -0,0 +1,232 @@
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
+| Date : Fri Jun 4 02:06:33 2021
+| Host : joan running 64-bit unknown
+| Command : report_utilization -file overlay_utilization_placed.rpt -pb overlay_utilization_placed.pb
+| Design : overlay
+| Device : 7z020clg400-1
+| Design State : Fully Placed
+-----------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++----------------------------+------+-------+-----------+-------+
+| Slice LUTs | 2985 | 0 | 53200 | 5.61 |
+| LUT as Logic | 2762 | 0 | 53200 | 5.19 |
+| LUT as Memory | 223 | 0 | 17400 | 1.28 |
+| LUT as Distributed RAM | 18 | 0 | | |
+| LUT as Shift Register | 205 | 0 | | |
+| Slice Registers | 4075 | 0 | 106400 | 3.83 |
+| Register as Flip Flop | 4075 | 0 | 106400 | 3.83 |
+| Register as Latch | 0 | 0 | 106400 | 0.00 |
+| F7 Muxes | 0 | 0 | 26600 | 0.00 |
+| F8 Muxes | 0 | 0 | 13300 | 0.00 |
++----------------------------+------+-------+-----------+-------+
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 33 | Yes | - | Set |
+| 69 | Yes | - | Reset |
+| 121 | Yes | Set | - |
+| 3852 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++--------------------------------------------+------+-------+-----------+-------+
+| Slice | 1342 | 0 | 13300 | 10.09 |
+| SLICEL | 820 | 0 | | |
+| SLICEM | 522 | 0 | | |
+| LUT as Logic | 2762 | 0 | 53200 | 5.19 |
+| using O5 output only | 0 | | | |
+| using O6 output only | 1979 | | | |
+| using O5 and O6 | 783 | | | |
+| LUT as Memory | 223 | 0 | 17400 | 1.28 |
+| LUT as Distributed RAM | 18 | 0 | | |
+| using O5 output only | 0 | | | |
+| using O6 output only | 2 | | | |
+| using O5 and O6 | 16 | | | |
+| LUT as Shift Register | 205 | 0 | | |
+| using O5 output only | 0 | | | |
+| using O6 output only | 125 | | | |
+| using O5 and O6 | 80 | | | |
+| Slice Registers | 4075 | 0 | 106400 | 3.83 |
+| Register driven from within the Slice | 2299 | | | |
+| Register driven from outside the Slice | 1776 | | | |
+| LUT in front of the register is unused | 1372 | | | |
+| LUT in front of the register is used | 404 | | | |
+| Unique Control Sets | 212 | | 13300 | 1.59 |
++--------------------------------------------+------+-------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++-------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-------------------+------+-------+-----------+-------+
+| Block RAM Tile | 2 | 0 | 140 | 1.43 |
+| RAMB36/FIFO* | 2 | 0 | 140 | 1.43 |
+| RAMB36E1 only | 2 | | | |
+| RAMB18 | 0 | 0 | 280 | 0.00 |
++-------------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs | 0 | 0 | 220 | 0.00 |
++-----------+------+-------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+--------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+--------+
+| Bonded IOB | 0 | 0 | 125 | 0.00 |
+| Bonded IPADs | 0 | 0 | 2 | 0.00 |
+| Bonded IOPADs | 130 | 130 | 130 | 100.00 |
+| PHY_CONTROL | 0 | 0 | 4 | 0.00 |
+| PHASER_REF | 0 | 0 | 4 | 0.00 |
+| OUT_FIFO | 0 | 0 | 16 | 0.00 |
+| IN_FIFO | 0 | 0 | 16 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 4 | 0.00 |
+| IBUFDS | 0 | 0 | 121 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 |
+| ILOGIC | 0 | 0 | 125 | 0.00 |
+| OLOGIC | 0 | 0 | 125 | 0.00 |
++-----------------------------+------+-------+-----------+--------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL | 1 | 0 | 32 | 3.13 |
+| BUFIO | 0 | 0 | 16 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 4 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 4 | 0.00 |
+| BUFMRCE | 0 | 0 | 8 | 0.00 |
+| BUFHCE | 0 | 0 | 72 | 0.00 |
+| BUFR | 0 | 0 | 16 | 0.00 |
++------------+------+-------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 2 | 0.00 |
+| STARTUPE2 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+----------------------+
+| Ref Name | Used | Functional Category |
++----------+------+----------------------+
+| FDRE | 3852 | Flop & Latch |
+| LUT3 | 1004 | LUT |
+| LUT6 | 790 | LUT |
+| LUT4 | 615 | LUT |
+| LUT5 | 584 | LUT |
+| LUT2 | 466 | LUT |
+| SRL16E | 196 | Distributed Memory |
+| BIBUF | 130 | IO |
+| FDSE | 121 | Flop & Latch |
+| CARRY4 | 93 | CarryLogic |
+| SRLC32E | 89 | Distributed Memory |
+| LUT1 | 86 | LUT |
+| FDCE | 69 | Flop & Latch |
+| FDPE | 33 | Flop & Latch |
+| RAMD32 | 26 | Distributed Memory |
+| RAMS32 | 8 | Distributed Memory |
+| RAMB36E1 | 2 | Block Memory |
+| PS7 | 1 | Specialized Resource |
+| BUFG | 1 | Clock |
++----------+------+----------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------------------+------+
+| Ref Name | Used |
++----------------------+------+
+| overlay_xbar_1 | 1 |
+| overlay_xbar_0 | 1 |
+| overlay_rst_ps_50M_0 | 1 |
+| overlay_ps_0 | 1 |
+| overlay_pixel_0 | 1 |
+| overlay_axi_dma_0_0 | 1 |
+| overlay_auto_us_1 | 1 |
+| overlay_auto_us_0 | 1 |
+| overlay_auto_pc_1 | 1 |
+| overlay_auto_pc_0 | 1 |
++----------------------+------+
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/phys_opt_design.pb b/rtl-proj/rtl.runs/impl_1/phys_opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..16ea37b2b70330c905cfc663abcaf39274612289
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/phys_opt_design.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/place_design.pb b/rtl-proj/rtl.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..7ac23e6d9192f88acec4a66d8d5c2b83d447ae27
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/place_design.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/project.wdf b/rtl-proj/rtl.runs/impl_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..67d501094ebd6fcebe77410c00dd386a19b61a29
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/project.wdf
@@ -0,0 +1,43 @@
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3131353966333462326366373435316161643236643862643837386238656431:506172656e742050412070726f6a656374204944:00
+eof:1162220011
diff --git a/rtl-proj/rtl.runs/impl_1/route_design.pb b/rtl-proj/rtl.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..fafe2dfbd21e427c0dea85553305d7ade497065b
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/route_design.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/rundef.js b/rtl-proj/rtl.runs/impl_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..3c71340366e6a97f2cfc5a9180e0c5120f72c30b
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/rundef.js
@@ -0,0 +1,44 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2020.2/bin;";
+} else {
+ PathVal = "/opt/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2020.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+ "-log overlay.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source overlay.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/rtl-proj/rtl.runs/impl_1/runme.bat b/rtl-proj/rtl.runs/impl_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..a3ce96cb599106f5a16d4c9d97fdfb9cb91fdc3a
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/rtl-proj/rtl.runs/impl_1/runme.log b/rtl-proj/rtl.runs/impl_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..5d9ecc3e3ffb81ef473fbfab4ecbfb61ad5892f0
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/runme.log
@@ -0,0 +1,685 @@
+
+*** Running vivado
+ with args -log overlay.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source overlay.tcl -notrace
+
+
+****** Vivado v2020.2 (64-bit)
+ **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+ **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+ ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+
+source overlay.tcl -notrace
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/mh02127/pixel_manipulation/embedded-security-project/hls-proj'.
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
+Command: link_design -top overlay -part xc7z020clg400-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7z020clg400-1
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.dcp' for cell 'axi_dma_0'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_pixel_0/overlay_pixel_0.dcp' for cell 'pixel'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_ps_0/overlay_ps_0.dcp' for cell 'ps'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0.dcp' for cell 'rst_ps_50M'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_xbar_1/overlay_xbar_1.dcp' for cell 'axi_mem_intercon/xbar'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_pc_1/overlay_auto_pc_1.dcp' for cell 'axi_mem_intercon/m00_couplers/auto_pc'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_0/overlay_auto_us_0.dcp' for cell 'axi_mem_intercon/s00_couplers/auto_us'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_1/overlay_auto_us_1.dcp' for cell 'axi_mem_intercon/s01_couplers/auto_us'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_xbar_0/overlay_xbar_0.dcp' for cell 'ps_axi_periph/xbar'
+INFO: [Project 1-454] Reading design checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_pc_0/overlay_auto_pc_0.dcp' for cell 'ps_axi_periph/s00_couplers/auto_pc'
+Netlist sorting complete. Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2288.238 ; gain = 0.000 ; free physical = 194621 ; free virtual = 207057
+INFO: [Netlist 29-17] Analyzing 108 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2020.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_ps_0/overlay_ps_0.xdc] for cell 'ps/inst'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_ps_0/overlay_ps_0.xdc] for cell 'ps/inst'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc] for cell 'axi_dma_0/U0'
+WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc:52]
+WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc:56]
+WARNING: [Vivado_Tcl 4-919] Waiver ID 'CDC-1' -from list should not be empty. [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc:61]
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0.xdc] for cell 'axi_dma_0/U0'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0_board.xdc] for cell 'rst_ps_50M/U0'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0_board.xdc] for cell 'rst_ps_50M/U0'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0.xdc] for cell 'rst_ps_50M/U0'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_rst_ps_50M_0/overlay_rst_ps_50M_0.xdc] for cell 'rst_ps_50M/U0'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0_clocks.xdc] for cell 'axi_dma_0/U0'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_axi_dma_0_0/overlay_axi_dma_0_0_clocks.xdc] for cell 'axi_dma_0/U0'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_0/overlay_auto_us_0_clocks.xdc] for cell 'axi_mem_intercon/s00_couplers/auto_us/inst'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_0/overlay_auto_us_0_clocks.xdc] for cell 'axi_mem_intercon/s00_couplers/auto_us/inst'
+Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_1/overlay_auto_us_1_clocks.xdc] for cell 'axi_mem_intercon/s01_couplers/auto_us/inst'
+Finished Parsing XDC File [/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.gen/sources_1/bd/overlay/ip/overlay_auto_us_1/overlay_auto_us_1_clocks.xdc] for cell 'axi_mem_intercon/s01_couplers/auto_us/inst'
+INFO: [Project 1-1715] 2 XPM XDC files have been applied to the design.
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2512.176 ; gain = 0.000 ; free physical = 193243 ; free virtual = 205679
+INFO: [Project 1-111] Unisim Transformation Summary:
+ A total of 5 instances were transformed.
+ RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 4 instances
+ RAM32X1D => RAM32X1D (RAMD32(x2)): 1 instance
+
+21 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2512.176 ; gain = 224.109 ; free physical = 193243 ; free virtual = 205679
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2512.176 ; gain = 0.000 ; free physical = 193984 ; free virtual = 206421
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 140cee8b3
+
+Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2650.078 ; gain = 137.902 ; free physical = 193614 ; free virtual = 206050
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 2 inverter(s) to 6 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 18b3a15e5
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193446 ; free virtual = 205882
+INFO: [Opt 31-389] Phase Retarget created 9 cells and removed 86 cells
+INFO: [Opt 31-1021] In phase Retarget, 24 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 2 inverter(s) to 9 load pin(s).
+Phase 2 Constant propagation | Checksum: 2242e1256
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193446 ; free virtual = 205882
+INFO: [Opt 31-389] Phase Constant propagation created 260 cells and removed 758 cells
+INFO: [Opt 31-1021] In phase Constant propagation, 24 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 1fc269322
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193442 ; free virtual = 205878
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 262 cells
+INFO: [Opt 31-1021] In phase Sweep, 96 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 1fc269322
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193428 ; free virtual = 205864
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 1fc269322
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193422 ; free virtual = 205859
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 1fc269322
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193419 ; free virtual = 205856
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+INFO: [Opt 31-1021] In phase Post Processing Netlist, 33 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 9 | 86 | 24 |
+| Constant propagation | 260 | 758 | 24 |
+| Sweep | 0 | 262 | 96 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 33 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193405 ; free virtual = 205841
+Ending Logic Optimization Task | Checksum: 1aebeab42
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2821.016 ; gain = 0.000 ; free physical = 193404 ; free virtual = 205841
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+INFO: [Pwropt 34-9] Applying IDT optimizations ...
+INFO: [Pwropt 34-10] Applying ODC optimizations ...
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+
+
+Starting PowerOpt Patch Enables Task
+INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 2 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
+INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
+Number of BRAM Ports augmented: 3 newly gated: 0 Total Ports: 4
+Ending PowerOpt Patch Enables Task | Checksum: 14bf263f5
+
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193367 ; free virtual = 205803
+Ending Power Optimization Task | Checksum: 14bf263f5
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3123.039 ; gain = 302.023 ; free physical = 193374 ; free virtual = 205810
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 14bf263f5
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193374 ; free virtual = 205810
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193374 ; free virtual = 205810
+Ending Netlist Obfuscation Task | Checksum: 19bdfcc68
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193374 ; free virtual = 205810
+INFO: [Common 17-83] Releasing license: Implementation
+47 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 3123.039 ; gain = 610.863 ; free physical = 193374 ; free virtual = 205810
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193366 ; free virtual = 205805
+INFO: [Common 17-1381] The checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file overlay_drc_opted.rpt -pb overlay_drc_opted.pb -rpx overlay_drc_opted.rpx
+Command: report_drc -file overlay_drc_opted.rpt -pb overlay_drc_opted.pb -rpx overlay_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Coretcl 2-168] The results of DRC are in file /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193267 ; free virtual = 205707
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c4dde10d
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193267 ; free virtual = 205707
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193267 ; free virtual = 205707
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 63597b98
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193292 ; free virtual = 205731
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: eab7f8df
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193293 ; free virtual = 205733
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: eab7f8df
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193293 ; free virtual = 205733
+Phase 1 Placer Initialization | Checksum: eab7f8df
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193292 ; free virtual = 205732
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 15eb4b930
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193276 ; free virtual = 205715
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: cdac8491
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193276 ; free virtual = 205716
+
+Phase 2.3 Global Placement Core
+
+Phase 2.3.1 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 349 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-775] End 1 Pass. Optimized 116 nets or cells. Created 0 new cell, deleted 116 existing cells and moved 0 existing cell
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193229 ; free virtual = 205668
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 116 | 116 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 116 | 116 | 0 | 3 | 00:00:01 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.3.1 Physical Synthesis In Placer | Checksum: 21643c6ce
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193227 ; free virtual = 205666
+Phase 2.3 Global Placement Core | Checksum: 13c2aa124
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193226 ; free virtual = 205665
+Phase 2 Global Placement | Checksum: 13c2aa124
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193226 ; free virtual = 205665
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 1ce0828fc
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:10 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193229 ; free virtual = 205669
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13619352c
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193224 ; free virtual = 205664
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1953488eb
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193224 ; free virtual = 205663
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 1f3f6e0cc
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:11 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193225 ; free virtual = 205664
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1539ebf56
+
+Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193385 ; free virtual = 205825
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: edf85c0a
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193377 ; free virtual = 205817
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 119290a8c
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193376 ; free virtual = 205816
+Phase 3 Detail Placement | Checksum: 119290a8c
+
+Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193375 ; free virtual = 205815
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 1b524cb9c
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.922 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 21ce08e3a
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.33 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193306 ; free virtual = 205746
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
+Ending Physical Synthesis Task | Checksum: 23e1a9a2d
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.38 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193328 ; free virtual = 205768
+Phase 4.1.1.1 BUFG Insertion | Checksum: 1b524cb9c
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193339 ; free virtual = 205779
+INFO: [Place 30-746] Post Placement Timing Summary WNS=9.922. For the most accurate timing information please run report_timing.
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193359 ; free virtual = 205799
+Phase 4.1 Post Commit Optimization | Checksum: 19d0c2147
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193380 ; free virtual = 205820
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 19d0c2147
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 19d0c2147
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+Phase 4.3 Placer Reporting | Checksum: 19d0c2147
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193383 ; free virtual = 205823
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: ce76e94c
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193382 ; free virtual = 205822
+Ending Placer Task | Checksum: 988376d7
+
+Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193381 ; free virtual = 205821
+INFO: [Common 17-83] Releasing license: Implementation
+82 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193404 ; free virtual = 205844
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.60 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193345 ; free virtual = 205797
+INFO: [Common 17-1381] The checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file overlay_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193347 ; free virtual = 205792
+INFO: [runtcl-4] Executing : report_utilization -file overlay_utilization_placed.rpt -pb overlay_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file overlay_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193398 ; free virtual = 205842
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+91 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193306 ; free virtual = 205761
+INFO: [Common 17-1381] The checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+Checksum: PlaceDB: 6f4628bd ConstDB: 0 ShapeSum: 293d4e1a RouteDB: 0
+
+Phase 1 Build RT Design
+Phase 1 Build RT Design | Checksum: 78af158c
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193308 ; free virtual = 205756
+Post Restoration Checksum: NetGraph: 41792313 NumContArr: 3735f279 Constraints: 0 Timing: 0
+
+Phase 2 Router Initialization
+
+Phase 2.1 Create Timer
+Phase 2.1 Create Timer | Checksum: 78af158c
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193310 ; free virtual = 205758
+
+Phase 2.2 Fix Topology Constraints
+Phase 2.2 Fix Topology Constraints | Checksum: 78af158c
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193276 ; free virtual = 205725
+
+Phase 2.3 Pre Route Cleanup
+Phase 2.3 Pre Route Cleanup | Checksum: 78af158c
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193276 ; free virtual = 205725
+ Number of Nodes with overlaps = 0
+
+Phase 2.4 Update Timing
+Phase 2.4 Update Timing | Checksum: a307ef69
+
+Time (s): cpu = 00:00:36 ; elapsed = 00:00:25 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 194006 ; free virtual = 206454
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=10.154 | TNS=0.000 | WHS=-0.329 | THS=-106.612|
+
+Phase 2 Router Initialization | Checksum: 3e4bd552
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:26 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193996 ; free virtual = 206444
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 6305
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 6305
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: 3e4bd552
+
+Time (s): cpu = 00:00:40 ; elapsed = 00:00:26 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193990 ; free virtual = 206438
+Phase 3 Initial Routing | Checksum: 15ea02df4
+
+Time (s): cpu = 00:00:43 ; elapsed = 00:00:27 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193957 ; free virtual = 206406
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 319
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.581 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 4.1 Global Iteration 0 | Checksum: 250dc868f
+
+Time (s): cpu = 00:00:49 ; elapsed = 00:00:29 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193972 ; free virtual = 206420
+
+Phase 4.2 Global Iteration 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.581 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 4.2 Global Iteration 1 | Checksum: f81c4f55
+
+Time (s): cpu = 00:00:50 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193961 ; free virtual = 206409
+Phase 4 Rip-up And Reroute | Checksum: f81c4f55
+
+Time (s): cpu = 00:00:50 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193961 ; free virtual = 206409
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+
+Phase 5.1.1 Update Timing
+Phase 5.1.1 Update Timing | Checksum: 124afa862
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193960 ; free virtual = 206408
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.581 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 5.1 Delay CleanUp | Checksum: 124afa862
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193960 ; free virtual = 206408
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: 124afa862
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193960 ; free virtual = 206408
+Phase 5 Delay and Skew Optimization | Checksum: 124afa862
+
+Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193960 ; free virtual = 206408
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 101bfc817
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193956 ; free virtual = 206404
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=9.581 | TNS=0.000 | WHS=0.030 | THS=0.000 |
+
+Phase 6.1 Hold Fix Iter | Checksum: 16a9da8f8
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193956 ; free virtual = 206404
+Phase 6 Post Hold Fix | Checksum: 16a9da8f8
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193956 ; free virtual = 206404
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 1.04857 %
+ Global Horizontal Routing Utilization = 1.19244 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 7 Route finalize | Checksum: fcdb8667
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193955 ; free virtual = 206403
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: fcdb8667
+
+Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 3123.039 ; gain = 0.000 ; free physical = 193954 ; free virtual = 206402
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: f5fb06ba
+
+Time (s): cpu = 00:00:57 ; elapsed = 00:00:32 . Memory (MB): peak = 3138.941 ; gain = 15.902 ; free physical = 193955 ; free virtual = 206403
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=9.581 | TNS=0.000 | WHS=0.030 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: f5fb06ba
+
+Time (s): cpu = 00:00:57 ; elapsed = 00:00:32 . Memory (MB): peak = 3138.941 ; gain = 15.902 ; free physical = 193956 ; free virtual = 206404
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:57 ; elapsed = 00:00:32 . Memory (MB): peak = 3138.941 ; gain = 15.902 ; free physical = 193993 ; free virtual = 206441
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+107 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:01:05 ; elapsed = 00:00:35 . Memory (MB): peak = 3138.941 ; gain = 15.902 ; free physical = 193993 ; free virtual = 206441
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 3138.941 ; gain = 0.000 ; free physical = 193965 ; free virtual = 206427
+INFO: [Common 17-1381] The checkpoint '/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file overlay_drc_routed.rpt -pb overlay_drc_routed.pb -rpx overlay_drc_routed.rpx
+Command: report_drc -file overlay_drc_routed.rpt -pb overlay_drc_routed.pb -rpx overlay_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Coretcl 2-168] The results of DRC are in file /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file overlay_methodology_drc_routed.rpt -pb overlay_methodology_drc_routed.pb -rpx overlay_methodology_drc_routed.rpx
+Command: report_methodology -file overlay_methodology_drc_routed.rpt -pb overlay_methodology_drc_routed.pb -rpx overlay_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file overlay_power_routed.rpt -pb overlay_power_summary_routed.pb -rpx overlay_power_routed.rpx
+Command: report_power -file overlay_power_routed.rpt -pb overlay_power_summary_routed.pb -rpx overlay_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
+Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
+119 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file overlay_route_status.rpt -pb overlay_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file overlay_timing_summary_routed.rpt -pb overlay_timing_summary_routed.pb -rpx overlay_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [runtcl-4] Executing : report_incremental_reuse -file overlay_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file overlay_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file overlay_bus_skew_routed.rpt -pb overlay_bus_skew_routed.pb -rpx overlay_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Memdata 28-167] Found XPM memory block axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block.
+INFO: [Memdata 28-208] The XPM instance: <axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <axi_dma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
+INFO: [Memdata 28-208] The XPM instance: <axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <axi_dma_0>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP.
+Command: write_bitstream -force overlay.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+WARNING: [DRC RTSTAT-10] No routable loads: 33 net(s) have no routable loads. The problem bus(es) and/or net(s) are axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i, axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0], axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0], axi_mem_intercon/m00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2:0]... and (the first 15 of 21 listed).
+INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
+INFO: [DRC REQP-181] writefirst: Synchronous clocking is detected for BRAM (axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg) in SDP mode with WRITE_FIRST write-mode. This is the preferred mode for best power characteristics, however it may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 2 Advisories
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./overlay.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
+INFO: [Common 17-83] Releasing license: Implementation
+17 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 3491.031 ; gain = 235.531 ; free physical = 193076 ; free virtual = 205537
+INFO: [Common 17-206] Exiting Vivado at Fri Jun 4 02:07:52 2021...
diff --git a/rtl-proj/rtl.runs/impl_1/runme.sh b/rtl-proj/rtl.runs/impl_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..269692e03c450caaefd9a2f9fe560bd2fb7d3e80
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/runme.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2020.2/bin
+else
+ PATH=/opt/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2020.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log overlay.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source overlay.tcl -notrace
+
+
diff --git a/rtl-proj/rtl.runs/impl_1/usage_statistics_webtalk.html b/rtl-proj/rtl.runs/impl_1/usage_statistics_webtalk.html
new file mode 100644
index 0000000000000000000000000000000000000000..8c9420e03d421fc2b10848b124153fcb630a1d0c
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/usage_statistics_webtalk.html
@@ -0,0 +1,1622 @@
+<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
+<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
+ <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Fri Jun 4 02:07:50 2021</TD>
+ <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>LIN64</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2020.2 (64-bit)</TD>
+ <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>1159f34b2cf7451aad26d8bd878b8ed1</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>1</TD>
+ <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>21f7b7be3f6659d59816e2858c345004</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>21f7b7be3f6659d59816e2858c345004</TD>
+ <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z020</TD>
+ <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg400</TD>
+ <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
+<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Xeon(R) CPU E5-2630 0 @ 2.30GHz</TD>
+ <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>1200.000 MHz</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>unknown</TD>
+ <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>unknown</TD>
+</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>236.000 GB</TD>
+ <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>2</TD>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
+<TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>guimode=1</TD>
+ <TD>tclmode=3</TD>
+</TR> </TABLE>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>constraintsetcount=0</TD>
+ <TD>core_container=false</TD>
+ <TD>currentimplrun=impl_1</TD>
+ <TD>currentsynthesisrun=synth_1</TD>
+</TR><TR ALIGN='LEFT'> <TD>default_library=xil_defaultlib</TD>
+ <TD>designmode=RTL</TD>
+ <TD>export_simulation_activehdl=0</TD>
+ <TD>export_simulation_ies=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>export_simulation_modelsim=0</TD>
+ <TD>export_simulation_questa=0</TD>
+ <TD>export_simulation_riviera=0</TD>
+ <TD>export_simulation_vcs=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>export_simulation_xsim=0</TD>
+ <TD>implstrategy=Vivado Implementation Defaults</TD>
+ <TD>launch_simulation_activehdl=0</TD>
+ <TD>launch_simulation_ies=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>launch_simulation_modelsim=0</TD>
+ <TD>launch_simulation_questa=0</TD>
+ <TD>launch_simulation_riviera=0</TD>
+ <TD>launch_simulation_vcs=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=0</TD>
+ <TD>simulator_language=Mixed</TD>
+ <TD>srcsetcount=1</TD>
+ <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
+</TR><TR ALIGN='LEFT'> <TD>target_language=Verilog</TD>
+ <TD>target_simulator=XSim</TD>
+ <TD>totalimplruns=11</TD>
+ <TD>totalsynthesisruns=11</TD>
+</TR> </TABLE>
+</TR> </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>bibuf=130</TD>
+ <TD>bufg=1</TD>
+ <TD>carry4=101</TD>
+ <TD>fdce=69</TD>
+</TR><TR ALIGN='LEFT'> <TD>fdpe=33</TD>
+ <TD>fdre=4265</TD>
+ <TD>fdse=122</TD>
+ <TD>gnd=175</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut1=162</TD>
+ <TD>lut2=491</TD>
+ <TD>lut3=1059</TD>
+ <TD>lut4=527</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut5=649</TD>
+ <TD>lut6=1053</TD>
+ <TD>ps7=1</TD>
+ <TD>ramb36e1=2</TD>
+</TR><TR ALIGN='LEFT'> <TD>ramd32=26</TD>
+ <TD>rams32=8</TD>
+ <TD>srl16e=193</TD>
+ <TD>srlc32e=106</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcc=178</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>bibuf=130</TD>
+ <TD>bufg=1</TD>
+ <TD>carry4=101</TD>
+ <TD>fdce=69</TD>
+</TR><TR ALIGN='LEFT'> <TD>fdpe=33</TD>
+ <TD>fdre=4265</TD>
+ <TD>fdse=122</TD>
+ <TD>gnd=175</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut1=162</TD>
+ <TD>lut2=491</TD>
+ <TD>lut3=1059</TD>
+ <TD>lut4=527</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut5=649</TD>
+ <TD>lut6=1053</TD>
+ <TD>ps7=1</TD>
+ <TD>ram32m=4</TD>
+</TR><TR ALIGN='LEFT'> <TD>ram32x1d=1</TD>
+ <TD>ramb36e1=2</TD>
+ <TD>srl16e=193</TD>
+ <TD>srlc32e=106</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcc=178</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>phys_opt_design_post_place</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>-aggressive_hold_fix=default::[not_specified]</TD>
+ <TD>-bram_register_opt=default::[not_specified]</TD>
+ <TD>-clock_opt=default::[not_specified]</TD>
+ <TD>-critical_cell_opt=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-critical_pin_opt=default::[not_specified]</TD>
+ <TD>-directive=default::[not_specified]</TD>
+ <TD>-dsp_register_opt=default::[not_specified]</TD>
+ <TD>-effort_level=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-fanout_opt=default::[not_specified]</TD>
+ <TD>-hold_fix=default::[not_specified]</TD>
+ <TD>-insert_negative_edge_ffs=default::[not_specified]</TD>
+ <TD>-multi_clock_opt=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-placement_opt=default::[not_specified]</TD>
+ <TD>-restruct_opt=default::[not_specified]</TD>
+ <TD>-retime=default::[not_specified]</TD>
+ <TD>-rewire=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-shift_register_opt=default::[not_specified]</TD>
+ <TD>-uram_register_opt=default::[not_specified]</TD>
+ <TD>-verbose=default::[not_specified]</TD>
+ <TD>-vhfn=default::[not_specified]</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>-cell_types=default::all</TD>
+ <TD>-clocks=default::[not_specified]</TD>
+ <TD>-exclude_cells=default::[not_specified]</TD>
+ <TD>-include_cells=default::[not_specified]</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>bram_ports_augmented=3</TD>
+ <TD>bram_ports_newly_gated=0</TD>
+ <TD>bram_ports_total=4</TD>
+ <TD>flow_state=default</TD>
+</TR><TR ALIGN='LEFT'> <TD>slice_registers_augmented=0</TD>
+ <TD>slice_registers_newly_gated=0</TD>
+ <TD>slice_registers_total=4075</TD>
+ <TD>srls_augmented=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>srls_newly_gated=0</TD>
+ <TD>srls_total=285</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>IP_Integrator/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>bdsource=USER</TD>
+ <TD>core_container=NA</TD>
+ <TD>da_axi4_cnt=4</TD>
+ <TD>da_ps7_cnt=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>iptotal=1</TD>
+ <TD>maxhierdepth=0</TD>
+ <TD>numblks=18</TD>
+ <TD>numhdlrefblks=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>numhierblks=8</TD>
+ <TD>numhlsblks=1</TD>
+ <TD>numnonxlnxblks=0</TD>
+ <TD>numpkgbdblks=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>numreposblks=10</TD>
+ <TD>numsysgenblks=0</TD>
+ <TD>synth_mode=OOC_per_IP</TD>
+ <TD>x_iplanguage=VERILOG</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplibrary=BlockDiagram</TD>
+ <TD>x_ipname=overlay</TD>
+ <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=1.00.a</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_crossbar_v2_1_23_axi_crossbar/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_axi_addr_width=32</TD>
+ <TD>c_axi_aruser_width=1</TD>
+ <TD>c_axi_awuser_width=1</TD>
+ <TD>c_axi_buser_width=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_data_width=32</TD>
+ <TD>c_axi_id_width=1</TD>
+ <TD>c_axi_protocol=2</TD>
+ <TD>c_axi_ruser_width=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_supports_user_signals=0</TD>
+ <TD>c_axi_wuser_width=1</TD>
+ <TD>c_connectivity_mode=0</TD>
+ <TD>c_family=zynq</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_addr_width=0x0000001000000010</TD>
+ <TD>c_m_axi_base_addr=0x00000000400000000000000041e00000</TD>
+ <TD>c_m_axi_read_connectivity=0xFFFFFFFFFFFFFFFF</TD>
+ <TD>c_m_axi_read_issuing=0x0000000100000001</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_secure=0x00000000</TD>
+ <TD>c_m_axi_write_connectivity=0xFFFFFFFFFFFFFFFF</TD>
+ <TD>c_m_axi_write_issuing=0x0000000100000001</TD>
+ <TD>c_num_addr_ranges=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_num_master_slots=2</TD>
+ <TD>c_num_slave_slots=1</TD>
+ <TD>c_r_register=1</TD>
+ <TD>c_s_axi_arb_priority=0x00000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_base_id=0x00000000</TD>
+ <TD>c_s_axi_read_acceptance=0x00000001</TD>
+ <TD>c_s_axi_single_thread=0x00000001</TD>
+ <TD>c_s_axi_thread_id_width=0x00000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_write_acceptance=0x00000001</TD>
+ <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>x_ipcorerevision=23</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplanguage=VERILOG</TD>
+ <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=axi_crossbar</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipsimlanguage=MIXED</TD>
+ <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=2.1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_crossbar_v2_1_23_axi_crossbar/2</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_axi_addr_width=32</TD>
+ <TD>c_axi_aruser_width=1</TD>
+ <TD>c_axi_awuser_width=1</TD>
+ <TD>c_axi_buser_width=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_data_width=64</TD>
+ <TD>c_axi_id_width=1</TD>
+ <TD>c_axi_protocol=0</TD>
+ <TD>c_axi_ruser_width=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_supports_user_signals=0</TD>
+ <TD>c_axi_wuser_width=1</TD>
+ <TD>c_connectivity_mode=1</TD>
+ <TD>c_family=zynq</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_addr_width=0x0000001d</TD>
+ <TD>c_m_axi_base_addr=0x0000000000000000</TD>
+ <TD>c_m_axi_read_connectivity=0x00000001</TD>
+ <TD>c_m_axi_read_issuing=0x00000008</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_secure=0x00000000</TD>
+ <TD>c_m_axi_write_connectivity=0x00000002</TD>
+ <TD>c_m_axi_write_issuing=0x00000008</TD>
+ <TD>c_num_addr_ranges=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_num_master_slots=1</TD>
+ <TD>c_num_slave_slots=2</TD>
+ <TD>c_r_register=0</TD>
+ <TD>c_s_axi_arb_priority=0x0000000000000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_base_id=0x0000000100000000</TD>
+ <TD>c_s_axi_read_acceptance=0x0000000200000008</TD>
+ <TD>c_s_axi_single_thread=0x0000000000000000</TD>
+ <TD>c_s_axi_thread_id_width=0x0000000000000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_write_acceptance=0x0000000800000002</TD>
+ <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>x_ipcorerevision=23</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplanguage=VERILOG</TD>
+ <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=axi_crossbar</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipsimlanguage=MIXED</TD>
+ <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=2.1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_dma/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_dlytmr_resolution=125</TD>
+ <TD>c_enable_multi_channel=0</TD>
+ <TD>c_family=zynq</TD>
+ <TD>c_include_mm2s=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_include_mm2s_dre=0</TD>
+ <TD>c_include_mm2s_sf=1</TD>
+ <TD>c_include_s2mm=1</TD>
+ <TD>c_include_s2mm_dre=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_include_s2mm_sf=1</TD>
+ <TD>c_include_sg=0</TD>
+ <TD>c_increase_throughput=0</TD>
+ <TD>c_m_axi_mm2s_addr_width=32</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_mm2s_data_width=32</TD>
+ <TD>c_m_axi_s2mm_addr_width=32</TD>
+ <TD>c_m_axi_s2mm_data_width=32</TD>
+ <TD>c_m_axi_sg_addr_width=32</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_sg_data_width=32</TD>
+ <TD>c_m_axis_mm2s_cntrl_tdata_width=32</TD>
+ <TD>c_m_axis_mm2s_tdata_width=32</TD>
+ <TD>c_micro_dma=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_mm2s_burst_size=16</TD>
+ <TD>c_num_mm2s_channels=1</TD>
+ <TD>c_num_s2mm_channels=1</TD>
+ <TD>c_prmry_is_aclk_async=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s2mm_burst_size=16</TD>
+ <TD>c_s_axi_lite_addr_width=10</TD>
+ <TD>c_s_axi_lite_data_width=32</TD>
+ <TD>c_s_axis_s2mm_sts_tdata_width=32</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axis_s2mm_tdata_width=32</TD>
+ <TD>c_sg_include_stscntrl_strm=0</TD>
+ <TD>c_sg_length_width=26</TD>
+ <TD>c_sg_use_stsapp_length=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>x_ipcorerevision=23</TD>
+ <TD>x_iplanguage=VERILOG</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=axi_dma</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+ <TD>x_ipsimlanguage=MIXED</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=7.1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_dwidth_converter_v2_1_22_top/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_axi_addr_width=32</TD>
+ <TD>c_axi_is_aclk_async=0</TD>
+ <TD>c_axi_protocol=0</TD>
+ <TD>c_axi_supports_read=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_supports_write=0</TD>
+ <TD>c_family=zynq</TD>
+ <TD>c_fifo_mode=0</TD>
+ <TD>c_m_axi_aclk_ratio=2</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_data_width=64</TD>
+ <TD>c_max_split_beats=16</TD>
+ <TD>c_packing_level=1</TD>
+ <TD>c_s_axi_aclk_ratio=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_data_width=32</TD>
+ <TD>c_s_axi_id_width=1</TD>
+ <TD>c_supports_id=0</TD>
+ <TD>c_synchronizer_stage=3</TD>
+</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>x_ipcorerevision=22</TD>
+ <TD>x_iplanguage=VERILOG</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=axi_dwidth_converter</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+ <TD>x_ipsimlanguage=MIXED</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=2.1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_dwidth_converter_v2_1_22_top/2</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_axi_addr_width=32</TD>
+ <TD>c_axi_is_aclk_async=0</TD>
+ <TD>c_axi_protocol=0</TD>
+ <TD>c_axi_supports_read=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_supports_write=1</TD>
+ <TD>c_family=zynq</TD>
+ <TD>c_fifo_mode=0</TD>
+ <TD>c_m_axi_aclk_ratio=2</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_data_width=64</TD>
+ <TD>c_max_split_beats=16</TD>
+ <TD>c_packing_level=1</TD>
+ <TD>c_s_axi_aclk_ratio=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_data_width=32</TD>
+ <TD>c_s_axi_id_width=1</TD>
+ <TD>c_supports_id=0</TD>
+ <TD>c_synchronizer_stage=3</TD>
+</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>x_ipcorerevision=22</TD>
+ <TD>x_iplanguage=VERILOG</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=axi_dwidth_converter</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+ <TD>x_ipsimlanguage=MIXED</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=2.1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_protocol_converter_v2_1_22_axi_protocol_converter/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_axi_addr_width=32</TD>
+ <TD>c_axi_aruser_width=1</TD>
+ <TD>c_axi_awuser_width=1</TD>
+ <TD>c_axi_buser_width=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_data_width=32</TD>
+ <TD>c_axi_id_width=12</TD>
+ <TD>c_axi_ruser_width=1</TD>
+ <TD>c_axi_supports_read=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_supports_user_signals=0</TD>
+ <TD>c_axi_supports_write=1</TD>
+ <TD>c_axi_wuser_width=1</TD>
+ <TD>c_family=zynq</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_ignore_id=0</TD>
+ <TD>c_m_axi_protocol=2</TD>
+ <TD>c_s_axi_protocol=1</TD>
+ <TD>c_translation_mode=2</TD>
+</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>x_ipcorerevision=22</TD>
+ <TD>x_iplanguage=VERILOG</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=axi_protocol_converter</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+ <TD>x_ipsimlanguage=MIXED</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=2.1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>axi_protocol_converter_v2_1_22_axi_protocol_converter/2</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_axi_addr_width=32</TD>
+ <TD>c_axi_aruser_width=1</TD>
+ <TD>c_axi_awuser_width=1</TD>
+ <TD>c_axi_buser_width=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_data_width=64</TD>
+ <TD>c_axi_id_width=1</TD>
+ <TD>c_axi_ruser_width=1</TD>
+ <TD>c_axi_supports_read=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_axi_supports_user_signals=0</TD>
+ <TD>c_axi_supports_write=1</TD>
+ <TD>c_axi_wuser_width=1</TD>
+ <TD>c_family=zynq</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_ignore_id=0</TD>
+ <TD>c_m_axi_protocol=1</TD>
+ <TD>c_s_axi_protocol=0</TD>
+ <TD>c_translation_mode=2</TD>
+</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>x_ipcorerevision=22</TD>
+ <TD>x_iplanguage=VERILOG</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=axi_protocol_converter</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+ <TD>x_ipsimlanguage=MIXED</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=2.1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>hls_ip_2020_2/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>hls_input_arch=others</TD>
+ <TD>hls_input_clock=10.000000</TD>
+ <TD>hls_input_fixed=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>hls_input_float=0</TD>
+ <TD>hls_input_part=xc7z020-clg400-1</TD>
+ <TD>hls_input_type=cxx</TD>
+ <TD>hls_syn_clock=6.723000</TD>
+</TR><TR ALIGN='LEFT'> <TD>hls_syn_dsp=0</TD>
+ <TD>hls_syn_ff=146</TD>
+ <TD>hls_syn_lat=1</TD>
+ <TD>hls_syn_lut=357</TD>
+</TR><TR ALIGN='LEFT'> <TD>hls_syn_mem=0</TD>
+ <TD>hls_syn_tpt=none</TD>
+ <TD>hls_version=2020_2</TD>
+ <TD>iptotal=1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pixel/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_s_axi_control_addr_width=6</TD>
+ <TD>c_s_axi_control_data_width=32</TD>
+ <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipcorerevision=2106040136</TD>
+ <TD>x_iplanguage=VERILOG</TD>
+ <TD>x_iplibrary=hls</TD>
+ <TD>x_ipname=pixel</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipproduct=Vivado 2020.2</TD>
+ <TD>x_ipsimlanguage=MIXED</TD>
+ <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=1.0</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>proc_sys_reset/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_aux_reset_high=0</TD>
+ <TD>c_aux_rst_width=4</TD>
+ <TD>c_ext_reset_high=0</TD>
+ <TD>c_ext_rst_width=4</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_family=zynq</TD>
+ <TD>c_num_bus_rst=1</TD>
+ <TD>c_num_interconnect_aresetn=1</TD>
+ <TD>c_num_perp_aresetn=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_num_perp_rst=1</TD>
+ <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>x_ipcorerevision=13</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplanguage=VERILOG</TD>
+ <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=proc_sys_reset</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipsimlanguage=MIXED</TD>
+ <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=5.0</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>processing_system7_v5.5_user_configuration/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>iptotal=1</TD>
+ <TD>pcw_apu_clk_ratio_enable=6:2:1</TD>
+ <TD>pcw_apu_peripheral_freqmhz=666.666666</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_armpll_ctrl_fbdiv=40</TD>
+ <TD>pcw_can0_grp_clk_enable=0</TD>
+ <TD>pcw_can0_peripheral_clksrc=External</TD>
+ <TD>pcw_can0_peripheral_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_can0_peripheral_freqmhz=-1</TD>
+ <TD>pcw_can1_grp_clk_enable=0</TD>
+ <TD>pcw_can1_peripheral_clksrc=External</TD>
+ <TD>pcw_can1_peripheral_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_can1_peripheral_freqmhz=-1</TD>
+ <TD>pcw_can_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_can_peripheral_freqmhz=100</TD>
+ <TD>pcw_cpu_cpu_pll_freqmhz=1333.333</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_cpu_peripheral_clksrc=ARM PLL</TD>
+ <TD>pcw_crystal_peripheral_freqmhz=33.333333</TD>
+ <TD>pcw_dci_peripheral_clksrc=DDR PLL</TD>
+ <TD>pcw_dci_peripheral_freqmhz=10.159</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ddr_ddr_pll_freqmhz=1066.667</TD>
+ <TD>pcw_ddr_hpr_to_critical_priority_level=15</TD>
+ <TD>pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)</TD>
+ <TD>pcw_ddr_lpr_to_critical_priority_level=2</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ddr_peripheral_clksrc=DDR PLL</TD>
+ <TD>pcw_ddr_port0_hpr_enable=0</TD>
+ <TD>pcw_ddr_port1_hpr_enable=0</TD>
+ <TD>pcw_ddr_port2_hpr_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ddr_port3_hpr_enable=0</TD>
+ <TD>pcw_ddr_write_to_critical_priority_level=2</TD>
+ <TD>pcw_ddrpll_ctrl_fbdiv=32</TD>
+ <TD>pcw_enet0_grp_mdio_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_enet0_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_enet0_peripheral_enable=0</TD>
+ <TD>pcw_enet0_peripheral_freqmhz=1000 Mbps</TD>
+ <TD>pcw_enet0_reset_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_enet1_grp_mdio_enable=0</TD>
+ <TD>pcw_enet1_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_enet1_peripheral_enable=0</TD>
+ <TD>pcw_enet1_peripheral_freqmhz=1000 Mbps</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_enet1_reset_enable=0</TD>
+ <TD>pcw_enet_reset_polarity=Active Low</TD>
+ <TD>pcw_fclk0_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_fclk1_peripheral_clksrc=IO PLL</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_fclk2_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_fclk3_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_fpga0_peripheral_freqmhz=50</TD>
+ <TD>pcw_fpga1_peripheral_freqmhz=50</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_fpga2_peripheral_freqmhz=50</TD>
+ <TD>pcw_fpga3_peripheral_freqmhz=50</TD>
+ <TD>pcw_fpga_fclk0_enable=1</TD>
+ <TD>pcw_fpga_fclk1_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_fpga_fclk2_enable=0</TD>
+ <TD>pcw_fpga_fclk3_enable=0</TD>
+ <TD>pcw_ftm_cti_in0=DISABLED</TD>
+ <TD>pcw_ftm_cti_in1=DISABLED</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ftm_cti_in2=DISABLED</TD>
+ <TD>pcw_ftm_cti_in3=DISABLED</TD>
+ <TD>pcw_ftm_cti_out0=DISABLED</TD>
+ <TD>pcw_ftm_cti_out1=DISABLED</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ftm_cti_out2=DISABLED</TD>
+ <TD>pcw_ftm_cti_out3=DISABLED</TD>
+ <TD>pcw_gpio_emio_gpio_enable=0</TD>
+ <TD>pcw_gpio_mio_gpio_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_gpio_peripheral_enable=0</TD>
+ <TD>pcw_i2c0_grp_int_enable=0</TD>
+ <TD>pcw_i2c0_peripheral_enable=0</TD>
+ <TD>pcw_i2c0_reset_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_i2c1_grp_int_enable=0</TD>
+ <TD>pcw_i2c1_peripheral_enable=0</TD>
+ <TD>pcw_i2c1_reset_enable=0</TD>
+ <TD>pcw_i2c_reset_polarity=Active Low</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_io_io_pll_freqmhz=1600.000</TD>
+ <TD>pcw_iopll_ctrl_fbdiv=48</TD>
+ <TD>pcw_irq_f2p_mode=DIRECT</TD>
+ <TD>pcw_m_axi_gp0_freqmhz=50</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_m_axi_gp1_freqmhz=10</TD>
+ <TD>pcw_nand_cycles_t_ar=1</TD>
+ <TD>pcw_nand_cycles_t_clr=1</TD>
+ <TD>pcw_nand_cycles_t_rc=11</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nand_cycles_t_rea=1</TD>
+ <TD>pcw_nand_cycles_t_rr=1</TD>
+ <TD>pcw_nand_cycles_t_wc=11</TD>
+ <TD>pcw_nand_cycles_t_wp=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nand_grp_d8_enable=0</TD>
+ <TD>pcw_nand_peripheral_enable=0</TD>
+ <TD>pcw_nor_cs0_t_ceoe=1</TD>
+ <TD>pcw_nor_cs0_t_pc=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_cs0_t_rc=11</TD>
+ <TD>pcw_nor_cs0_t_tr=1</TD>
+ <TD>pcw_nor_cs0_t_wc=11</TD>
+ <TD>pcw_nor_cs0_t_wp=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_cs0_we_time=0</TD>
+ <TD>pcw_nor_cs1_t_ceoe=1</TD>
+ <TD>pcw_nor_cs1_t_pc=1</TD>
+ <TD>pcw_nor_cs1_t_rc=11</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_cs1_t_tr=1</TD>
+ <TD>pcw_nor_cs1_t_wc=11</TD>
+ <TD>pcw_nor_cs1_t_wp=1</TD>
+ <TD>pcw_nor_cs1_we_time=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_grp_a25_enable=0</TD>
+ <TD>pcw_nor_grp_cs0_enable=0</TD>
+ <TD>pcw_nor_grp_cs1_enable=0</TD>
+ <TD>pcw_nor_grp_sram_cs0_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_grp_sram_cs1_enable=0</TD>
+ <TD>pcw_nor_grp_sram_int_enable=0</TD>
+ <TD>pcw_nor_peripheral_enable=0</TD>
+ <TD>pcw_nor_sram_cs0_t_ceoe=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_sram_cs0_t_pc=1</TD>
+ <TD>pcw_nor_sram_cs0_t_rc=11</TD>
+ <TD>pcw_nor_sram_cs0_t_tr=1</TD>
+ <TD>pcw_nor_sram_cs0_t_wc=11</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_sram_cs0_t_wp=1</TD>
+ <TD>pcw_nor_sram_cs0_we_time=0</TD>
+ <TD>pcw_nor_sram_cs1_t_ceoe=1</TD>
+ <TD>pcw_nor_sram_cs1_t_pc=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_sram_cs1_t_rc=11</TD>
+ <TD>pcw_nor_sram_cs1_t_tr=1</TD>
+ <TD>pcw_nor_sram_cs1_t_wc=11</TD>
+ <TD>pcw_nor_sram_cs1_t_wp=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_nor_sram_cs1_we_time=0</TD>
+ <TD>pcw_override_basic_clock=0</TD>
+ <TD>pcw_pcap_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_pcap_peripheral_freqmhz=200</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_pjtag_peripheral_enable=0</TD>
+ <TD>pcw_preset_bank0_voltage=LVCMOS 3.3V</TD>
+ <TD>pcw_preset_bank1_voltage=LVCMOS 3.3V</TD>
+ <TD>pcw_qspi_grp_fbclk_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_qspi_grp_io1_enable=0</TD>
+ <TD>pcw_qspi_grp_single_ss_enable=0</TD>
+ <TD>pcw_qspi_grp_ss1_enable=0</TD>
+ <TD>pcw_qspi_internal_highaddress=0xFCFFFFFF</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_qspi_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_qspi_peripheral_enable=0</TD>
+ <TD>pcw_qspi_peripheral_freqmhz=200</TD>
+ <TD>pcw_s_axi_acp_freqmhz=10</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_s_axi_gp0_freqmhz=10</TD>
+ <TD>pcw_s_axi_gp1_freqmhz=10</TD>
+ <TD>pcw_s_axi_hp0_data_width=64</TD>
+ <TD>pcw_s_axi_hp0_freqmhz=50</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_s_axi_hp1_data_width=64</TD>
+ <TD>pcw_s_axi_hp1_freqmhz=10</TD>
+ <TD>pcw_s_axi_hp2_data_width=64</TD>
+ <TD>pcw_s_axi_hp2_freqmhz=10</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_s_axi_hp3_data_width=64</TD>
+ <TD>pcw_s_axi_hp3_freqmhz=10</TD>
+ <TD>pcw_sd0_grp_cd_enable=0</TD>
+ <TD>pcw_sd0_grp_pow_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_sd0_grp_wp_enable=0</TD>
+ <TD>pcw_sd0_peripheral_enable=0</TD>
+ <TD>pcw_sd1_grp_cd_enable=0</TD>
+ <TD>pcw_sd1_grp_pow_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_sd1_grp_wp_enable=0</TD>
+ <TD>pcw_sd1_peripheral_enable=0</TD>
+ <TD>pcw_sdio_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_sdio_peripheral_freqmhz=100</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_smc_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_smc_peripheral_freqmhz=100</TD>
+ <TD>pcw_spi0_grp_ss0_enable=0</TD>
+ <TD>pcw_spi0_grp_ss1_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_spi0_grp_ss2_enable=0</TD>
+ <TD>pcw_spi0_peripheral_enable=0</TD>
+ <TD>pcw_spi1_grp_ss0_enable=0</TD>
+ <TD>pcw_spi1_grp_ss1_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_spi1_grp_ss2_enable=0</TD>
+ <TD>pcw_spi1_peripheral_enable=0</TD>
+ <TD>pcw_spi_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_spi_peripheral_freqmhz=166.666666</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_tpiu_peripheral_clksrc=External</TD>
+ <TD>pcw_tpiu_peripheral_freqmhz=200</TD>
+ <TD>pcw_trace_grp_16bit_enable=0</TD>
+ <TD>pcw_trace_grp_2bit_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_trace_grp_32bit_enable=0</TD>
+ <TD>pcw_trace_grp_4bit_enable=0</TD>
+ <TD>pcw_trace_grp_8bit_enable=0</TD>
+ <TD>pcw_trace_peripheral_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ttc0_clk0_peripheral_clksrc=CPU_1X</TD>
+ <TD>pcw_ttc0_clk0_peripheral_freqmhz=133.333333</TD>
+ <TD>pcw_ttc0_clk1_peripheral_clksrc=CPU_1X</TD>
+ <TD>pcw_ttc0_clk1_peripheral_freqmhz=133.333333</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ttc0_clk2_peripheral_clksrc=CPU_1X</TD>
+ <TD>pcw_ttc0_clk2_peripheral_freqmhz=133.333333</TD>
+ <TD>pcw_ttc0_peripheral_enable=0</TD>
+ <TD>pcw_ttc1_clk0_peripheral_clksrc=CPU_1X</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ttc1_clk0_peripheral_freqmhz=133.333333</TD>
+ <TD>pcw_ttc1_clk1_peripheral_clksrc=CPU_1X</TD>
+ <TD>pcw_ttc1_clk1_peripheral_freqmhz=133.333333</TD>
+ <TD>pcw_ttc1_clk2_peripheral_clksrc=CPU_1X</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_ttc1_clk2_peripheral_freqmhz=133.333333</TD>
+ <TD>pcw_ttc1_peripheral_enable=0</TD>
+ <TD>pcw_ttc_peripheral_freqmhz=50</TD>
+ <TD>pcw_uart0_baud_rate=115200</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uart0_grp_full_enable=0</TD>
+ <TD>pcw_uart0_peripheral_enable=0</TD>
+ <TD>pcw_uart1_baud_rate=115200</TD>
+ <TD>pcw_uart1_grp_full_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uart1_peripheral_enable=0</TD>
+ <TD>pcw_uart_peripheral_clksrc=IO PLL</TD>
+ <TD>pcw_uart_peripheral_freqmhz=100</TD>
+ <TD>pcw_uiparam_ddr_adv_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_al=0</TD>
+ <TD>pcw_uiparam_ddr_bank_addr_count=3</TD>
+ <TD>pcw_uiparam_ddr_bl=8</TD>
+ <TD>pcw_uiparam_ddr_board_delay0=0.25</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_board_delay1=0.25</TD>
+ <TD>pcw_uiparam_ddr_board_delay2=0.25</TD>
+ <TD>pcw_uiparam_ddr_board_delay3=0.25</TD>
+ <TD>pcw_uiparam_ddr_bus_width=32 Bit</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_cl=7</TD>
+ <TD>pcw_uiparam_ddr_clock_0_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_clock_0_package_length=80.4535</TD>
+ <TD>pcw_uiparam_ddr_clock_0_propogation_delay=160</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_clock_1_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_clock_1_package_length=80.4535</TD>
+ <TD>pcw_uiparam_ddr_clock_1_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_clock_2_length_mm=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_clock_2_package_length=80.4535</TD>
+ <TD>pcw_uiparam_ddr_clock_2_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_clock_3_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_clock_3_package_length=80.4535</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_clock_3_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_clock_stop_en=0</TD>
+ <TD>pcw_uiparam_ddr_col_addr_count=10</TD>
+ <TD>pcw_uiparam_ddr_cwl=6</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_device_capacity=1024 MBits</TD>
+ <TD>pcw_uiparam_ddr_dq_0_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_dq_0_package_length=98.503</TD>
+ <TD>pcw_uiparam_ddr_dq_0_propogation_delay=160</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_dq_1_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_dq_1_package_length=68.5855</TD>
+ <TD>pcw_uiparam_ddr_dq_1_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_dq_2_length_mm=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_dq_2_package_length=90.295</TD>
+ <TD>pcw_uiparam_ddr_dq_2_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_dq_3_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_dq_3_package_length=103.977</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_dq_3_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_dqs_0_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_dqs_0_package_length=105.056</TD>
+ <TD>pcw_uiparam_ddr_dqs_0_propogation_delay=160</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_dqs_1_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_dqs_1_package_length=66.904</TD>
+ <TD>pcw_uiparam_ddr_dqs_1_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_dqs_2_length_mm=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_dqs_2_package_length=89.1715</TD>
+ <TD>pcw_uiparam_ddr_dqs_2_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_dqs_3_length_mm=0</TD>
+ <TD>pcw_uiparam_ddr_dqs_3_package_length=113.63</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_dqs_3_propogation_delay=160</TD>
+ <TD>pcw_uiparam_ddr_dqs_to_clk_delay_0=0.0</TD>
+ <TD>pcw_uiparam_ddr_dqs_to_clk_delay_1=0.0</TD>
+ <TD>pcw_uiparam_ddr_dqs_to_clk_delay_2=0.0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_dqs_to_clk_delay_3=0.0</TD>
+ <TD>pcw_uiparam_ddr_dram_width=8 Bits</TD>
+ <TD>pcw_uiparam_ddr_ecc=Disabled</TD>
+ <TD>pcw_uiparam_ddr_enable=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_freq_mhz=533.333333</TD>
+ <TD>pcw_uiparam_ddr_high_temp=Normal (0-85)</TD>
+ <TD>pcw_uiparam_ddr_memory_type=DDR 3</TD>
+ <TD>pcw_uiparam_ddr_partno=MT41J128M8 JP-125</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_row_addr_count=14</TD>
+ <TD>pcw_uiparam_ddr_speed_bin=DDR3_1066F</TD>
+ <TD>pcw_uiparam_ddr_t_faw=30.0</TD>
+ <TD>pcw_uiparam_ddr_t_ras_min=35.0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_t_rc=48.75</TD>
+ <TD>pcw_uiparam_ddr_t_rcd=7</TD>
+ <TD>pcw_uiparam_ddr_t_rp=7</TD>
+ <TD>pcw_uiparam_ddr_train_data_eye=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_uiparam_ddr_train_read_gate=1</TD>
+ <TD>pcw_uiparam_ddr_train_write_level=1</TD>
+ <TD>pcw_uiparam_ddr_use_internal_vref=0</TD>
+ <TD>pcw_usb0_peripheral_enable=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_usb0_peripheral_freqmhz=60</TD>
+ <TD>pcw_usb0_reset_enable=0</TD>
+ <TD>pcw_usb1_peripheral_enable=0</TD>
+ <TD>pcw_usb1_peripheral_freqmhz=60</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_usb1_reset_enable=0</TD>
+ <TD>pcw_usb_reset_polarity=Active Low</TD>
+ <TD>pcw_use_cross_trigger=0</TD>
+ <TD>pcw_use_m_axi_gp0=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_use_m_axi_gp1=0</TD>
+ <TD>pcw_use_s_axi_acp=0</TD>
+ <TD>pcw_use_s_axi_gp0=0</TD>
+ <TD>pcw_use_s_axi_gp1=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_use_s_axi_hp0=1</TD>
+ <TD>pcw_use_s_axi_hp1=0</TD>
+ <TD>pcw_use_s_axi_hp2=0</TD>
+ <TD>pcw_use_s_axi_hp3=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>pcw_wdt_peripheral_clksrc=CPU_1X</TD>
+ <TD>pcw_wdt_peripheral_enable=0</TD>
+ <TD>pcw_wdt_peripheral_freqmhz=133.333333</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>processing_system7_v5_5_processing_system7/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>c_dm_width=4</TD>
+ <TD>c_dq_width=32</TD>
+ <TD>c_dqs_width=4</TD>
+ <TD>c_emio_gpio_width=64</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_en_emio_enet0=0</TD>
+ <TD>c_en_emio_enet1=0</TD>
+ <TD>c_en_emio_pjtag=0</TD>
+ <TD>c_en_emio_trace=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_fclk_clk0_buf=TRUE</TD>
+ <TD>c_fclk_clk1_buf=FALSE</TD>
+ <TD>c_fclk_clk2_buf=FALSE</TD>
+ <TD>c_fclk_clk3_buf=FALSE</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_gp0_en_modifiable_txn=1</TD>
+ <TD>c_gp1_en_modifiable_txn=1</TD>
+ <TD>c_include_acp_trans_check=0</TD>
+ <TD>c_include_trace_buffer=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_irq_f2p_mode=DIRECT</TD>
+ <TD>c_m_axi_gp0_enable_static_remap=0</TD>
+ <TD>c_m_axi_gp0_id_width=12</TD>
+ <TD>c_m_axi_gp0_thread_id_width=12</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_m_axi_gp1_enable_static_remap=0</TD>
+ <TD>c_m_axi_gp1_id_width=12</TD>
+ <TD>c_m_axi_gp1_thread_id_width=12</TD>
+ <TD>c_mio_primitive=54</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_num_f2p_intr_inputs=1</TD>
+ <TD>c_package_name=clg400</TD>
+ <TD>c_ps7_si_rev=PRODUCTION</TD>
+ <TD>c_s_axi_acp_aruser_val=31</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_acp_awuser_val=31</TD>
+ <TD>c_s_axi_acp_id_width=3</TD>
+ <TD>c_s_axi_gp0_id_width=6</TD>
+ <TD>c_s_axi_gp1_id_width=6</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_hp0_data_width=64</TD>
+ <TD>c_s_axi_hp0_id_width=6</TD>
+ <TD>c_s_axi_hp1_data_width=64</TD>
+ <TD>c_s_axi_hp1_id_width=6</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_s_axi_hp2_data_width=64</TD>
+ <TD>c_s_axi_hp2_id_width=6</TD>
+ <TD>c_s_axi_hp3_data_width=64</TD>
+ <TD>c_s_axi_hp3_id_width=6</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_trace_buffer_clock_delay=12</TD>
+ <TD>c_trace_buffer_fifo_size=128</TD>
+ <TD>c_trace_internal_width=2</TD>
+ <TD>c_trace_pipeline_width=8</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_use_axi_nonsecure=0</TD>
+ <TD>c_use_default_acp_user_val=0</TD>
+ <TD>c_use_m_axi_gp0=1</TD>
+ <TD>c_use_m_axi_gp1=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_use_s_axi_acp=0</TD>
+ <TD>c_use_s_axi_gp0=0</TD>
+ <TD>c_use_s_axi_gp1=0</TD>
+ <TD>c_use_s_axi_hp0=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>c_use_s_axi_hp1=0</TD>
+ <TD>c_use_s_axi_hp2=0</TD>
+ <TD>c_use_s_axi_hp3=0</TD>
+ <TD>core_container=NA</TD>
+</TR><TR ALIGN='LEFT'> <TD>iptotal=1</TD>
+ <TD>use_trace_data_edge_detector=0</TD>
+ <TD>x_ipcorerevision=6</TD>
+ <TD>x_iplanguage=VERILOG</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_iplibrary=ip</TD>
+ <TD>x_ipname=processing_system7</TD>
+ <TD>x_ipproduct=Vivado 2020.2</TD>
+ <TD>x_ipsimlanguage=MIXED</TD>
+</TR><TR ALIGN='LEFT'> <TD>x_ipvendor=xilinx.com</TD>
+ <TD>x_ipversion=5.5</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_cdc_async_rst/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>def_val=1'b0</TD>
+ <TD>dest_sync_ff=2</TD>
+ <TD>init_sync_ff=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>inv_def_val=1'b1</TD>
+ <TD>iptotal=3</TD>
+ <TD>rst_active_high=1</TD>
+ <TD>version=0</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_fifo_base/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>both_stages_valid=3</TD>
+ <TD>cascade_height=0</TD>
+ <TD>cdc_dest_sync_ff=2</TD>
+ <TD>common_clock=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>dout_reset_value=0</TD>
+ <TD>ecc_mode=0</TD>
+ <TD>en_adv_feature=16'b0001111100011111</TD>
+</TR><TR ALIGN='LEFT'> <TD>en_ae=1'b1</TD>
+ <TD>en_af=1'b1</TD>
+ <TD>en_dvld=1'b1</TD>
+ <TD>en_of=1'b1</TD>
+</TR><TR ALIGN='LEFT'> <TD>en_pe=1'b1</TD>
+ <TD>en_pf=1'b1</TD>
+ <TD>en_rdc=1'b1</TD>
+ <TD>en_uf=1'b1</TD>
+</TR><TR ALIGN='LEFT'> <TD>en_wack=1'b1</TD>
+ <TD>en_wdc=1'b1</TD>
+ <TD>enable_ecc=0</TD>
+ <TD>fg_eq_asym_dout=1'b0</TD>
+</TR><TR ALIGN='LEFT'> <TD>fifo_mem_type=0</TD>
+ <TD>fifo_memory_type=0</TD>
+ <TD>fifo_read_depth=16</TD>
+ <TD>fifo_read_latency=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>fifo_size=144</TD>
+ <TD>fifo_write_depth=16</TD>
+ <TD>full_reset_value=1</TD>
+ <TD>full_rst_val=1'b1</TD>
+</TR><TR ALIGN='LEFT'> <TD>invalid=0</TD>
+ <TD>iptotal=3</TD>
+ <TD>pe_thresh_adj=8</TD>
+ <TD>pe_thresh_max=11</TD>
+</TR><TR ALIGN='LEFT'> <TD>pe_thresh_min=5</TD>
+ <TD>pf_thresh_adj=8</TD>
+ <TD>pf_thresh_max=11</TD>
+ <TD>pf_thresh_min=5</TD>
+</TR><TR ALIGN='LEFT'> <TD>prog_empty_thresh=10</TD>
+ <TD>prog_full_thresh=10</TD>
+ <TD>rd_data_count_width=4</TD>
+ <TD>rd_dc_width_ext=5</TD>
+</TR><TR ALIGN='LEFT'> <TD>rd_latency=2</TD>
+ <TD>rd_mode=1</TD>
+ <TD>rd_pntr_width=4</TD>
+ <TD>read_data_width=9</TD>
+</TR><TR ALIGN='LEFT'> <TD>read_mode=1</TD>
+ <TD>read_mode_ll=1</TD>
+ <TD>related_clocks=0</TD>
+ <TD>remove_wr_rd_prot_logic=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>sim_assert_chk=0</TD>
+ <TD>stage1_valid=2</TD>
+ <TD>stage2_valid=1</TD>
+ <TD>use_adv_features=1F1F</TD>
+</TR><TR ALIGN='LEFT'> <TD>version=0</TD>
+ <TD>wakeup_time=0</TD>
+ <TD>width_ratio=1</TD>
+ <TD>wr_data_count_width=5</TD>
+</TR><TR ALIGN='LEFT'> <TD>wr_dc_width_ext=5</TD>
+ <TD>wr_depth_log=4</TD>
+ <TD>wr_pntr_width=4</TD>
+ <TD>wr_rd_ratio=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>wr_width_log=4</TD>
+ <TD>write_data_width=9</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_fifo_sync/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>cascade_height=0</TD>
+ <TD>core_container=NA</TD>
+ <TD>dout_reset_value=0</TD>
+ <TD>ecc_mode=no_ecc</TD>
+</TR><TR ALIGN='LEFT'> <TD>en_adv_feature_sync=16'b0001111100011111</TD>
+ <TD>fifo_memory_type=auto</TD>
+ <TD>fifo_read_latency=0</TD>
+ <TD>fifo_write_depth=16</TD>
+</TR><TR ALIGN='LEFT'> <TD>full_reset_value=1</TD>
+ <TD>iptotal=3</TD>
+ <TD>p_common_clock=1</TD>
+ <TD>p_ecc_mode=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>p_fifo_memory_type=0</TD>
+ <TD>p_read_mode=1</TD>
+ <TD>p_wakeup_time=2</TD>
+ <TD>prog_empty_thresh=10</TD>
+</TR><TR ALIGN='LEFT'> <TD>prog_full_thresh=10</TD>
+ <TD>rd_data_count_width=4</TD>
+ <TD>read_data_width=9</TD>
+ <TD>read_mode=fwft</TD>
+</TR><TR ALIGN='LEFT'> <TD>sim_assert_chk=0</TD>
+ <TD>use_adv_features=1F1F</TD>
+ <TD>wakeup_time=0</TD>
+ <TD>wr_data_count_width=5</TD>
+</TR><TR ALIGN='LEFT'> <TD>write_data_width=9</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xpm_memory_base/1</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>write_data_width=9</TD>
+ <TD>addr_width_a=4</TD>
+ <TD>addr_width_b=4</TD>
+ <TD>auto_sleep_time=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>byte_write_width_a=9</TD>
+ <TD>byte_write_width_b=9</TD>
+ <TD>cascade_height=0</TD>
+ <TD>clocking_mode=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>core_container=NA</TD>
+ <TD>ecc_mode=0</TD>
+ <TD>iptotal=3</TD>
+ <TD>max_num_char=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>memory_optimization=true</TD>
+ <TD>memory_primitive=0</TD>
+ <TD>memory_size=144</TD>
+ <TD>memory_type=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>message_control=0</TD>
+ <TD>num_char_loc=0</TD>
+ <TD>p_ecc_mode=no_ecc</TD>
+ <TD>p_enable_byte_write_a=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>p_enable_byte_write_b=0</TD>
+ <TD>p_max_depth_data=16</TD>
+ <TD>p_memory_opt=yes</TD>
+ <TD>p_memory_primitive=auto</TD>
+</TR><TR ALIGN='LEFT'> <TD>p_min_width_data=9</TD>
+ <TD>p_min_width_data_a=9</TD>
+ <TD>p_min_width_data_b=9</TD>
+ <TD>p_min_width_data_ecc=9</TD>
+</TR><TR ALIGN='LEFT'> <TD>p_min_width_data_ldw=4</TD>
+ <TD>p_min_width_data_shft=9</TD>
+ <TD>p_num_cols_write_a=1</TD>
+ <TD>p_num_cols_write_b=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>p_num_rows_read_a=1</TD>
+ <TD>p_num_rows_read_b=1</TD>
+ <TD>p_num_rows_write_a=1</TD>
+ <TD>p_num_rows_write_b=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>p_sdp_write_mode=yes</TD>
+ <TD>p_width_addr_lsb_read_a=0</TD>
+ <TD>p_width_addr_lsb_read_b=0</TD>
+ <TD>p_width_addr_lsb_write_a=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>p_width_addr_lsb_write_b=0</TD>
+ <TD>p_width_addr_read_a=4</TD>
+ <TD>p_width_addr_read_b=4</TD>
+ <TD>p_width_addr_write_a=4</TD>
+</TR><TR ALIGN='LEFT'> <TD>p_width_addr_write_b=4</TD>
+ <TD>p_width_col_write_a=9</TD>
+ <TD>p_width_col_write_b=9</TD>
+ <TD>read_data_width_a=9</TD>
+</TR><TR ALIGN='LEFT'> <TD>read_data_width_b=9</TD>
+ <TD>read_latency_a=2</TD>
+ <TD>read_latency_b=2</TD>
+ <TD>read_reset_value_a=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>read_reset_value_b=0</TD>
+ <TD>rst_mode_a=SYNC</TD>
+ <TD>rst_mode_b=SYNC</TD>
+ <TD>rsta_loop_iter=12</TD>
+</TR><TR ALIGN='LEFT'> <TD>rstb_loop_iter=12</TD>
+ <TD>sim_assert_chk=0</TD>
+ <TD>use_embedded_constraint=0</TD>
+ <TD>use_mem_init=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>use_mem_init_mmi=0</TD>
+ <TD>version=0</TD>
+ <TD>wakeup_time=0</TD>
+ <TD>write_data_width_a=9</TD>
+</TR><TR ALIGN='LEFT'> <TD>write_data_width_b=9</TD>
+ <TD>write_mode_a=2</TD>
+ <TD>write_mode_b=2</TD>
+ <TD>write_protect=1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
+ <TD>-checks=default::[not_specified]</TD>
+ <TD>-fail_on=default::[not_specified]</TD>
+ <TD>-force=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
+ <TD>-internal=default::[not_specified]</TD>
+ <TD>-internal_only=default::[not_specified]</TD>
+ <TD>-max_msgs_per_check=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-messages=default::[not_specified]</TD>
+ <TD>-name=default::[not_specified]</TD>
+ <TD>-no_waivers=default::[not_specified]</TD>
+ <TD>-return_string=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-ruledecks=default::[not_specified]</TD>
+ <TD>-upgrade_cw=default::[not_specified]</TD>
+ <TD>-waived=default::[not_specified]</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>reqp-181=2</TD>
+ <TD>rtstat-10=1</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
+ <TD>-checks=default::[not_specified]</TD>
+ <TD>-fail_on=default::[not_specified]</TD>
+ <TD>-force=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
+ <TD>-messages=default::[not_specified]</TD>
+ <TD>-name=default::[not_specified]</TD>
+ <TD>-return_string=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-slack_lesser_than=default::[not_specified]</TD>
+ <TD>-waived=default::[not_specified]</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>lutar-1=3</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>-advisory=default::[not_specified]</TD>
+ <TD>-append=default::[not_specified]</TD>
+ <TD>-file=[specified]</TD>
+ <TD>-format=default::text</TD>
+</TR><TR ALIGN='LEFT'> <TD>-hier=default::power</TD>
+ <TD>-hierarchical_depth=default::4</TD>
+ <TD>-l=default::[not_specified]</TD>
+ <TD>-name=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-no_propagation=default::[not_specified]</TD>
+ <TD>-return_string=default::[not_specified]</TD>
+ <TD>-rpx=[specified]</TD>
+ <TD>-verbose=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-vid=default::[not_specified]</TD>
+ <TD>-xpe=default::[not_specified]</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>airflow=250 (LFM)</TD>
+ <TD>ambient_temp=25.0 (C)</TD>
+ <TD>bi-dir_toggle=12.500000</TD>
+ <TD>bidir_output_enable=1.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>board_layers=8to11 (8 to 11 Layers)</TD>
+ <TD>board_selection=medium (10"x10")</TD>
+ <TD>bram=0.000048</TD>
+ <TD>clocks=0.007783</TD>
+</TR><TR ALIGN='LEFT'> <TD>confidence_level_clock_activity=High</TD>
+ <TD>confidence_level_design_state=High</TD>
+ <TD>confidence_level_device_models=High</TD>
+ <TD>confidence_level_internal_activity=Medium</TD>
+</TR><TR ALIGN='LEFT'> <TD>confidence_level_io_activity=High</TD>
+ <TD>confidence_level_overall=Medium</TD>
+ <TD>customer=TBD</TD>
+ <TD>customer_class=TBD</TD>
+</TR><TR ALIGN='LEFT'> <TD>devstatic=0.136176</TD>
+ <TD>die=xc7z020clg400-1</TD>
+ <TD>dsp_output_toggle=12.500000</TD>
+ <TD>dynamic=1.537895</TD>
+</TR><TR ALIGN='LEFT'> <TD>effective_thetaja=11.53</TD>
+ <TD>enable_probability=0.990000</TD>
+ <TD>family=zynq</TD>
+ <TD>ff_toggle=12.500000</TD>
+</TR><TR ALIGN='LEFT'> <TD>flow_state=routed</TD>
+ <TD>heatsink=none</TD>
+ <TD>input_toggle=12.500000</TD>
+ <TD>junction_temp=44.3 (C)</TD>
+</TR><TR ALIGN='LEFT'> <TD>logic=0.001146</TD>
+ <TD>mgtavcc_dynamic_current=0.000000</TD>
+ <TD>mgtavcc_static_current=0.000000</TD>
+ <TD>mgtavcc_total_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>mgtavcc_voltage=1.000000</TD>
+ <TD>mgtavtt_dynamic_current=0.000000</TD>
+ <TD>mgtavtt_static_current=0.000000</TD>
+ <TD>mgtavtt_total_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>mgtavtt_voltage=1.200000</TD>
+ <TD>mgtvccaux_dynamic_current=0.000000</TD>
+ <TD>mgtvccaux_static_current=0.000000</TD>
+ <TD>mgtvccaux_total_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>mgtvccaux_voltage=1.800000</TD>
+ <TD>netlist_net_matched=NA</TD>
+ <TD>off-chip_power=0.000000</TD>
+ <TD>on-chip_power=1.674070</TD>
+</TR><TR ALIGN='LEFT'> <TD>output_enable=1.000000</TD>
+ <TD>output_load=5.000000</TD>
+ <TD>output_toggle=12.500000</TD>
+ <TD>package=clg400</TD>
+</TR><TR ALIGN='LEFT'> <TD>pct_clock_constrained=6.480000</TD>
+ <TD>pct_inputs_defined=0</TD>
+ <TD>platform=lin64</TD>
+ <TD>process=typical</TD>
+</TR><TR ALIGN='LEFT'> <TD>ps7=1.527332</TD>
+ <TD>ram_enable=50.000000</TD>
+ <TD>ram_write=50.000000</TD>
+ <TD>read_saif=False</TD>
+</TR><TR ALIGN='LEFT'> <TD>set/reset_probability=0.000000</TD>
+ <TD>signal_rate=False</TD>
+ <TD>signals=0.001586</TD>
+ <TD>simulation_file=None</TD>
+</TR><TR ALIGN='LEFT'> <TD>speedgrade=-1</TD>
+ <TD>static_prob=False</TD>
+ <TD>temp_grade=commercial</TD>
+ <TD>thetajb=7.4 (C/W)</TD>
+</TR><TR ALIGN='LEFT'> <TD>thetasa=0.0 (C/W)</TD>
+ <TD>toggle_rate=False</TD>
+ <TD>user_board_temp=25.0 (C)</TD>
+ <TD>user_effective_thetaja=11.53</TD>
+</TR><TR ALIGN='LEFT'> <TD>user_junc_temp=44.3 (C)</TD>
+ <TD>user_thetajb=7.4 (C/W)</TD>
+ <TD>user_thetasa=0.0 (C/W)</TD>
+ <TD>vccadc_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vccadc_static_current=0.020000</TD>
+ <TD>vccadc_total_current=0.020000</TD>
+ <TD>vccadc_voltage=1.800000</TD>
+ <TD>vccaux_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vccaux_io_dynamic_current=0.000000</TD>
+ <TD>vccaux_io_static_current=0.000000</TD>
+ <TD>vccaux_io_total_current=0.000000</TD>
+ <TD>vccaux_io_voltage=1.800000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vccaux_static_current=0.015149</TD>
+ <TD>vccaux_total_current=0.015149</TD>
+ <TD>vccaux_voltage=1.800000</TD>
+ <TD>vccbram_dynamic_current=0.000001</TD>
+</TR><TR ALIGN='LEFT'> <TD>vccbram_static_current=0.001026</TD>
+ <TD>vccbram_total_current=0.001027</TD>
+ <TD>vccbram_voltage=1.000000</TD>
+ <TD>vccint_dynamic_current=0.010561</TD>
+</TR><TR ALIGN='LEFT'> <TD>vccint_static_current=0.014849</TD>
+ <TD>vccint_total_current=0.025411</TD>
+ <TD>vccint_voltage=1.000000</TD>
+ <TD>vcco12_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco12_static_current=0.000000</TD>
+ <TD>vcco12_total_current=0.000000</TD>
+ <TD>vcco12_voltage=1.200000</TD>
+ <TD>vcco135_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco135_static_current=0.000000</TD>
+ <TD>vcco135_total_current=0.000000</TD>
+ <TD>vcco135_voltage=1.350000</TD>
+ <TD>vcco15_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco15_static_current=0.000000</TD>
+ <TD>vcco15_total_current=0.000000</TD>
+ <TD>vcco15_voltage=1.500000</TD>
+ <TD>vcco18_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco18_static_current=0.000000</TD>
+ <TD>vcco18_total_current=0.000000</TD>
+ <TD>vcco18_voltage=1.800000</TD>
+ <TD>vcco25_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco25_static_current=0.000000</TD>
+ <TD>vcco25_total_current=0.000000</TD>
+ <TD>vcco25_voltage=2.500000</TD>
+ <TD>vcco33_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco33_static_current=0.000000</TD>
+ <TD>vcco33_total_current=0.000000</TD>
+ <TD>vcco33_voltage=3.300000</TD>
+ <TD>vcco_ddr_dynamic_current=0.456904</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco_ddr_static_current=0.002000</TD>
+ <TD>vcco_ddr_total_current=0.458904</TD>
+ <TD>vcco_ddr_voltage=1.500000</TD>
+ <TD>vcco_mio0_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco_mio0_static_current=0.000000</TD>
+ <TD>vcco_mio0_total_current=0.000000</TD>
+ <TD>vcco_mio0_voltage=1.800000</TD>
+ <TD>vcco_mio1_dynamic_current=0.000000</TD>
+</TR><TR ALIGN='LEFT'> <TD>vcco_mio1_static_current=0.000000</TD>
+ <TD>vcco_mio1_total_current=0.000000</TD>
+ <TD>vcco_mio1_voltage=1.800000</TD>
+ <TD>vccpaux_dynamic_current=0.050131</TD>
+</TR><TR ALIGN='LEFT'> <TD>vccpaux_static_current=0.010330</TD>
+ <TD>vccpaux_total_current=0.060461</TD>
+ <TD>vccpaux_voltage=1.800000</TD>
+ <TD>vccpint_dynamic_current=0.723985</TD>
+</TR><TR ALIGN='LEFT'> <TD>vccpint_static_current=0.030037</TD>
+ <TD>vccpint_total_current=0.754023</TD>
+ <TD>vccpint_voltage=1.000000</TD>
+ <TD>vccpll_dynamic_current=0.015420</TD>
+</TR><TR ALIGN='LEFT'> <TD>vccpll_static_current=0.003000</TD>
+ <TD>vccpll_total_current=0.018420</TD>
+ <TD>vccpll_voltage=1.800000</TD>
+ <TD>version=2020.2</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
+ <TD>bufgctrl_fixed=0</TD>
+ <TD>bufgctrl_used=1</TD>
+ <TD>bufgctrl_util_percentage=3.13</TD>
+</TR><TR ALIGN='LEFT'> <TD>bufhce_available=72</TD>
+ <TD>bufhce_fixed=0</TD>
+ <TD>bufhce_used=0</TD>
+ <TD>bufhce_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>bufio_available=16</TD>
+ <TD>bufio_fixed=0</TD>
+ <TD>bufio_used=0</TD>
+ <TD>bufio_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>bufmrce_available=8</TD>
+ <TD>bufmrce_fixed=0</TD>
+ <TD>bufmrce_used=0</TD>
+ <TD>bufmrce_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>bufr_available=16</TD>
+ <TD>bufr_fixed=0</TD>
+ <TD>bufr_used=0</TD>
+ <TD>bufr_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_available=4</TD>
+ <TD>mmcme2_adv_fixed=0</TD>
+ <TD>mmcme2_adv_used=0</TD>
+ <TD>mmcme2_adv_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>plle2_adv_available=4</TD>
+ <TD>plle2_adv_fixed=0</TD>
+ <TD>plle2_adv_used=0</TD>
+ <TD>plle2_adv_util_percentage=0.00</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>dsps_available=220</TD>
+ <TD>dsps_fixed=0</TD>
+ <TD>dsps_used=0</TD>
+ <TD>dsps_util_percentage=0.00</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>blvds_25=0</TD>
+ <TD>diff_hstl_i=0</TD>
+ <TD>diff_hstl_i_18=0</TD>
+ <TD>diff_hstl_ii=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>diff_hstl_ii_18=0</TD>
+ <TD>diff_hsul_12=0</TD>
+ <TD>diff_mobile_ddr=0</TD>
+ <TD>diff_sstl135=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>diff_sstl135_r=0</TD>
+ <TD>diff_sstl15=1</TD>
+ <TD>diff_sstl15_r=0</TD>
+ <TD>diff_sstl18_i=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>diff_sstl18_ii=0</TD>
+ <TD>hstl_i=0</TD>
+ <TD>hstl_i_18=0</TD>
+ <TD>hstl_ii=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>hstl_ii_18=0</TD>
+ <TD>hsul_12=0</TD>
+ <TD>lvcmos12=0</TD>
+ <TD>lvcmos15=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>lvcmos18=1</TD>
+ <TD>lvcmos25=0</TD>
+ <TD>lvcmos33=1</TD>
+ <TD>lvds_25=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>lvttl=0</TD>
+ <TD>mini_lvds_25=0</TD>
+ <TD>mobile_ddr=0</TD>
+ <TD>pci33_3=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>ppds_25=0</TD>
+ <TD>rsds_25=0</TD>
+ <TD>sstl135=0</TD>
+ <TD>sstl135_r=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>sstl15=1</TD>
+ <TD>sstl15_r=0</TD>
+ <TD>sstl18_i=0</TD>
+ <TD>sstl18_ii=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>tmds_33=0</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>block_ram_tile_available=140</TD>
+ <TD>block_ram_tile_fixed=0</TD>
+ <TD>block_ram_tile_used=2</TD>
+ <TD>block_ram_tile_util_percentage=1.43</TD>
+</TR><TR ALIGN='LEFT'> <TD>ramb18_available=280</TD>
+ <TD>ramb18_fixed=0</TD>
+ <TD>ramb18_used=0</TD>
+ <TD>ramb18_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_available=140</TD>
+ <TD>ramb36_fifo_fixed=0</TD>
+ <TD>ramb36_fifo_used=2</TD>
+ <TD>ramb36_fifo_util_percentage=1.43</TD>
+</TR><TR ALIGN='LEFT'> <TD>ramb36e1_only_used=2</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>bibuf_functional_category=IO</TD>
+ <TD>bibuf_used=130</TD>
+ <TD>bufg_functional_category=Clock</TD>
+ <TD>bufg_used=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>carry4_functional_category=CarryLogic</TD>
+ <TD>carry4_used=93</TD>
+ <TD>fdce_functional_category=Flop & Latch</TD>
+ <TD>fdce_used=69</TD>
+</TR><TR ALIGN='LEFT'> <TD>fdpe_functional_category=Flop & Latch</TD>
+ <TD>fdpe_used=33</TD>
+ <TD>fdre_functional_category=Flop & Latch</TD>
+ <TD>fdre_used=3852</TD>
+</TR><TR ALIGN='LEFT'> <TD>fdse_functional_category=Flop & Latch</TD>
+ <TD>fdse_used=121</TD>
+ <TD>lut1_functional_category=LUT</TD>
+ <TD>lut1_used=86</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut2_functional_category=LUT</TD>
+ <TD>lut2_used=466</TD>
+ <TD>lut3_functional_category=LUT</TD>
+ <TD>lut3_used=1004</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut4_functional_category=LUT</TD>
+ <TD>lut4_used=615</TD>
+ <TD>lut5_functional_category=LUT</TD>
+ <TD>lut5_used=584</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut6_functional_category=LUT</TD>
+ <TD>lut6_used=790</TD>
+ <TD>ps7_functional_category=Specialized Resource</TD>
+ <TD>ps7_used=1</TD>
+</TR><TR ALIGN='LEFT'> <TD>ramb36e1_functional_category=Block Memory</TD>
+ <TD>ramb36e1_used=2</TD>
+ <TD>ramd32_functional_category=Distributed Memory</TD>
+ <TD>ramd32_used=26</TD>
+</TR><TR ALIGN='LEFT'> <TD>rams32_functional_category=Distributed Memory</TD>
+ <TD>rams32_used=8</TD>
+ <TD>srl16e_functional_category=Distributed Memory</TD>
+ <TD>srl16e_used=196</TD>
+</TR><TR ALIGN='LEFT'> <TD>srlc32e_functional_category=Distributed Memory</TD>
+ <TD>srlc32e_used=89</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>f7_muxes_available=26600</TD>
+ <TD>f7_muxes_fixed=0</TD>
+ <TD>f7_muxes_used=0</TD>
+ <TD>f7_muxes_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=13300</TD>
+ <TD>f8_muxes_fixed=0</TD>
+ <TD>f8_muxes_used=0</TD>
+ <TD>f8_muxes_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut_as_distributed_ram_fixed=0</TD>
+ <TD>lut_as_distributed_ram_used=18</TD>
+ <TD>lut_as_logic_available=53200</TD>
+ <TD>lut_as_logic_fixed=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_used=2762</TD>
+ <TD>lut_as_logic_util_percentage=5.19</TD>
+ <TD>lut_as_memory_available=17400</TD>
+ <TD>lut_as_memory_fixed=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_used=223</TD>
+ <TD>lut_as_memory_util_percentage=1.28</TD>
+ <TD>lut_as_shift_register_fixed=0</TD>
+ <TD>lut_as_shift_register_used=205</TD>
+</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=106400</TD>
+ <TD>register_as_flip_flop_fixed=0</TD>
+ <TD>register_as_flip_flop_used=4075</TD>
+ <TD>register_as_flip_flop_util_percentage=3.83</TD>
+</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=106400</TD>
+ <TD>register_as_latch_fixed=0</TD>
+ <TD>register_as_latch_used=0</TD>
+ <TD>register_as_latch_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=53200</TD>
+ <TD>slice_luts_fixed=0</TD>
+ <TD>slice_luts_used=2985</TD>
+ <TD>slice_luts_util_percentage=5.61</TD>
+</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=106400</TD>
+ <TD>slice_registers_fixed=0</TD>
+ <TD>slice_registers_used=4075</TD>
+ <TD>slice_registers_util_percentage=3.83</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut_as_distributed_ram_fixed=0</TD>
+ <TD>lut_as_distributed_ram_used=18</TD>
+ <TD>lut_as_logic_available=53200</TD>
+ <TD>lut_as_logic_fixed=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_used=2762</TD>
+ <TD>lut_as_logic_util_percentage=5.19</TD>
+ <TD>lut_as_memory_available=17400</TD>
+ <TD>lut_as_memory_fixed=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_used=223</TD>
+ <TD>lut_as_memory_util_percentage=1.28</TD>
+ <TD>lut_as_shift_register_fixed=0</TD>
+ <TD>lut_as_shift_register_used=205</TD>
+</TR><TR ALIGN='LEFT'> <TD>lut_in_front_of_the_register_is_unused_fixed=205</TD>
+ <TD>lut_in_front_of_the_register_is_unused_used=1372</TD>
+ <TD>lut_in_front_of_the_register_is_used_fixed=1372</TD>
+ <TD>lut_in_front_of_the_register_is_used_used=404</TD>
+</TR><TR ALIGN='LEFT'> <TD>register_driven_from_outside_the_slice_fixed=404</TD>
+ <TD>register_driven_from_outside_the_slice_used=1776</TD>
+ <TD>register_driven_from_within_the_slice_fixed=1776</TD>
+ <TD>register_driven_from_within_the_slice_used=2299</TD>
+</TR><TR ALIGN='LEFT'> <TD>slice_available=13300</TD>
+ <TD>slice_fixed=0</TD>
+ <TD>slice_registers_available=106400</TD>
+ <TD>slice_registers_fixed=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>slice_registers_used=4075</TD>
+ <TD>slice_registers_util_percentage=3.83</TD>
+ <TD>slice_used=1342</TD>
+ <TD>slice_util_percentage=10.09</TD>
+</TR><TR ALIGN='LEFT'> <TD>slicel_fixed=0</TD>
+ <TD>slicel_used=820</TD>
+ <TD>slicem_fixed=0</TD>
+ <TD>slicem_used=522</TD>
+</TR><TR ALIGN='LEFT'> <TD>unique_control_sets_available=13300</TD>
+ <TD>unique_control_sets_fixed=13300</TD>
+ <TD>unique_control_sets_used=212</TD>
+ <TD>unique_control_sets_util_percentage=1.59</TD>
+</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_fixed=1.59</TD>
+ <TD>using_o5_and_o6_used=80</TD>
+ <TD>using_o5_output_only_fixed=80</TD>
+ <TD>using_o5_output_only_used=0</TD>
+</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_fixed=0</TD>
+ <TD>using_o6_output_only_used=125</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>bscane2_available=4</TD>
+ <TD>bscane2_fixed=0</TD>
+ <TD>bscane2_used=0</TD>
+ <TD>bscane2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>capturee2_available=1</TD>
+ <TD>capturee2_fixed=0</TD>
+ <TD>capturee2_used=0</TD>
+ <TD>capturee2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>dna_port_available=1</TD>
+ <TD>dna_port_fixed=0</TD>
+ <TD>dna_port_used=0</TD>
+ <TD>dna_port_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>efuse_usr_available=1</TD>
+ <TD>efuse_usr_fixed=0</TD>
+ <TD>efuse_usr_used=0</TD>
+ <TD>efuse_usr_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>frame_ecce2_available=1</TD>
+ <TD>frame_ecce2_fixed=0</TD>
+ <TD>frame_ecce2_used=0</TD>
+ <TD>frame_ecce2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>icape2_available=2</TD>
+ <TD>icape2_fixed=0</TD>
+ <TD>icape2_used=0</TD>
+ <TD>icape2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>startupe2_available=1</TD>
+ <TD>startupe2_fixed=0</TD>
+ <TD>startupe2_used=0</TD>
+ <TD>startupe2_util_percentage=0.00</TD>
+</TR><TR ALIGN='LEFT'> <TD>xadc_available=1</TD>
+ <TD>xadc_fixed=0</TD>
+ <TD>xadc_used=0</TD>
+ <TD>xadc_util_percentage=0.00</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>-assert=default::[not_specified]</TD>
+ <TD>-bufg=default::12</TD>
+ <TD>-cascade_dsp=default::auto</TD>
+ <TD>-constrset=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-control_set_opt_threshold=default::auto</TD>
+ <TD>-debug_log=default::[not_specified]</TD>
+ <TD>-directive=default::default</TD>
+ <TD>-fanout_limit=default::10000</TD>
+</TR><TR ALIGN='LEFT'> <TD>-flatten_hierarchy=default::rebuilt</TD>
+ <TD>-fsm_extraction=default::auto</TD>
+ <TD>-gated_clock_conversion=default::off</TD>
+ <TD>-generic=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-include_dirs=default::[not_specified]</TD>
+ <TD>-keep_equivalent_registers=default::[not_specified]</TD>
+ <TD>-lint=default::[not_specified]</TD>
+ <TD>-max_bram=default::-1</TD>
+</TR><TR ALIGN='LEFT'> <TD>-max_bram_cascade_height=default::-1</TD>
+ <TD>-max_dsp=default::-1</TD>
+ <TD>-max_uram=default::-1</TD>
+ <TD>-max_uram_cascade_height=default::-1</TD>
+</TR><TR ALIGN='LEFT'> <TD>-mode=default::default</TD>
+ <TD>-name=default::[not_specified]</TD>
+ <TD>-no_lc=default::[not_specified]</TD>
+ <TD>-no_srlextract=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-no_timing_driven=default::[not_specified]</TD>
+ <TD>-os=default::[not_specified]</TD>
+ <TD>-part=xc7z020clg400-1</TD>
+ <TD>-resource_sharing=default::auto</TD>
+</TR><TR ALIGN='LEFT'> <TD>-retiming=default::[not_specified]</TD>
+ <TD>-rtl=default::[not_specified]</TD>
+ <TD>-rtl_skip_constraints=default::[not_specified]</TD>
+ <TD>-rtl_skip_ip=default::[not_specified]</TD>
+</TR><TR ALIGN='LEFT'> <TD>-seu_protect=default::none</TD>
+ <TD>-sfcu=default::[not_specified]</TD>
+ <TD>-shreg_min_size=default::3</TD>
+ <TD>-top=overlay</TD>
+</TR><TR ALIGN='LEFT'> <TD>-verilog_define=default::[not_specified]</TD>
+</TR> </TABLE>
+ </TD></TR>
+ <TR><TD>
+ <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
+ <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
+<TR ALIGN='LEFT'> <TD>elapsed=00:00:34s</TD>
+ <TD>hls_ip=0</TD>
+ <TD>memory_gain=64.031MB</TD>
+ <TD>memory_peak=2352.094MB</TD>
+</TR> </TABLE>
+ </TD></TR>
+ </TABLE><BR>
+</BODY>
+</HTML>
diff --git a/rtl-proj/rtl.runs/impl_1/usage_statistics_webtalk.xml b/rtl-proj/rtl.runs/impl_1/usage_statistics_webtalk.xml
new file mode 100644
index 0000000000000000000000000000000000000000..8d6c55e90f215bb14806b9e49f15090eebdba6e9
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/usage_statistics_webtalk.xml
@@ -0,0 +1,1498 @@
+<?xml version="1.0" encoding="UTF-8" ?>
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+ <keyValuePair key="core_container" value="NA" description="" />
+ <keyValuePair key="iptotal" value="1" description="" />
+ <keyValuePair key="x_ipcorerevision" value="13" description="" />
+ <keyValuePair key="x_iplanguage" value="VERILOG" description="" />
+ <keyValuePair key="x_iplibrary" value="ip" description="" />
+ <keyValuePair key="x_ipname" value="proc_sys_reset" description="" />
+ <keyValuePair key="x_ipproduct" value="Vivado 2020.2" description="" />
+ <keyValuePair key="x_ipsimlanguage" value="MIXED" description="" />
+ <keyValuePair key="x_ipvendor" value="xilinx.com" description="" />
+ <keyValuePair key="x_ipversion" value="5.0" description="" />
+ </section>
+ <section name="processing_system7_v5.5_user_configuration/1" level="2" order="12" description="">
+ <keyValuePair key="core_container" value="NA" description="" />
+ <keyValuePair key="iptotal" value="1" description="" />
+ <keyValuePair key="pcw_apu_clk_ratio_enable" value="6:2:1" description="" />
+ <keyValuePair key="pcw_apu_peripheral_freqmhz" value="666.666666" description="" />
+ <keyValuePair key="pcw_armpll_ctrl_fbdiv" value="40" description="" />
+ <keyValuePair key="pcw_can0_grp_clk_enable" value="0" description="" />
+ <keyValuePair key="pcw_can0_peripheral_clksrc" value="External" description="" />
+ <keyValuePair key="pcw_can0_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_can0_peripheral_freqmhz" value="-1" description="" />
+ <keyValuePair key="pcw_can1_grp_clk_enable" value="0" description="" />
+ <keyValuePair key="pcw_can1_peripheral_clksrc" value="External" description="" />
+ <keyValuePair key="pcw_can1_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_can1_peripheral_freqmhz" value="-1" description="" />
+ <keyValuePair key="pcw_can_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_can_peripheral_freqmhz" value="100" description="" />
+ <keyValuePair key="pcw_cpu_cpu_pll_freqmhz" value="1333.333" description="" />
+ <keyValuePair key="pcw_cpu_peripheral_clksrc" value="ARM PLL" description="" />
+ <keyValuePair key="pcw_crystal_peripheral_freqmhz" value="33.333333" description="" />
+ <keyValuePair key="pcw_dci_peripheral_clksrc" value="DDR PLL" description="" />
+ <keyValuePair key="pcw_dci_peripheral_freqmhz" value="10.159" description="" />
+ <keyValuePair key="pcw_ddr_ddr_pll_freqmhz" value="1066.667" description="" />
+ <keyValuePair key="pcw_ddr_hpr_to_critical_priority_level" value="15" description="" />
+ <keyValuePair key="pcw_ddr_hprlpr_queue_partition" value="HPR(0)/LPR(32)" description="" />
+ <keyValuePair key="pcw_ddr_lpr_to_critical_priority_level" value="2" description="" />
+ <keyValuePair key="pcw_ddr_peripheral_clksrc" value="DDR PLL" description="" />
+ <keyValuePair key="pcw_ddr_port0_hpr_enable" value="0" description="" />
+ <keyValuePair key="pcw_ddr_port1_hpr_enable" value="0" description="" />
+ <keyValuePair key="pcw_ddr_port2_hpr_enable" value="0" description="" />
+ <keyValuePair key="pcw_ddr_port3_hpr_enable" value="0" description="" />
+ <keyValuePair key="pcw_ddr_write_to_critical_priority_level" value="2" description="" />
+ <keyValuePair key="pcw_ddrpll_ctrl_fbdiv" value="32" description="" />
+ <keyValuePair key="pcw_enet0_grp_mdio_enable" value="0" description="" />
+ <keyValuePair key="pcw_enet0_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_enet0_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_enet0_peripheral_freqmhz" value="1000 Mbps" description="" />
+ <keyValuePair key="pcw_enet0_reset_enable" value="0" description="" />
+ <keyValuePair key="pcw_enet1_grp_mdio_enable" value="0" description="" />
+ <keyValuePair key="pcw_enet1_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_enet1_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_enet1_peripheral_freqmhz" value="1000 Mbps" description="" />
+ <keyValuePair key="pcw_enet1_reset_enable" value="0" description="" />
+ <keyValuePair key="pcw_enet_reset_polarity" value="Active Low" description="" />
+ <keyValuePair key="pcw_fclk0_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_fclk1_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_fclk2_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_fclk3_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_fpga0_peripheral_freqmhz" value="50" description="" />
+ <keyValuePair key="pcw_fpga1_peripheral_freqmhz" value="50" description="" />
+ <keyValuePair key="pcw_fpga2_peripheral_freqmhz" value="50" description="" />
+ <keyValuePair key="pcw_fpga3_peripheral_freqmhz" value="50" description="" />
+ <keyValuePair key="pcw_fpga_fclk0_enable" value="1" description="" />
+ <keyValuePair key="pcw_fpga_fclk1_enable" value="0" description="" />
+ <keyValuePair key="pcw_fpga_fclk2_enable" value="0" description="" />
+ <keyValuePair key="pcw_fpga_fclk3_enable" value="0" description="" />
+ <keyValuePair key="pcw_ftm_cti_in0" value="DISABLED" description="" />
+ <keyValuePair key="pcw_ftm_cti_in1" value="DISABLED" description="" />
+ <keyValuePair key="pcw_ftm_cti_in2" value="DISABLED" description="" />
+ <keyValuePair key="pcw_ftm_cti_in3" value="DISABLED" description="" />
+ <keyValuePair key="pcw_ftm_cti_out0" value="DISABLED" description="" />
+ <keyValuePair key="pcw_ftm_cti_out1" value="DISABLED" description="" />
+ <keyValuePair key="pcw_ftm_cti_out2" value="DISABLED" description="" />
+ <keyValuePair key="pcw_ftm_cti_out3" value="DISABLED" description="" />
+ <keyValuePair key="pcw_gpio_emio_gpio_enable" value="0" description="" />
+ <keyValuePair key="pcw_gpio_mio_gpio_enable" value="0" description="" />
+ <keyValuePair key="pcw_gpio_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_i2c0_grp_int_enable" value="0" description="" />
+ <keyValuePair key="pcw_i2c0_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_i2c0_reset_enable" value="0" description="" />
+ <keyValuePair key="pcw_i2c1_grp_int_enable" value="0" description="" />
+ <keyValuePair key="pcw_i2c1_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_i2c1_reset_enable" value="0" description="" />
+ <keyValuePair key="pcw_i2c_reset_polarity" value="Active Low" description="" />
+ <keyValuePair key="pcw_io_io_pll_freqmhz" value="1600.000" description="" />
+ <keyValuePair key="pcw_iopll_ctrl_fbdiv" value="48" description="" />
+ <keyValuePair key="pcw_irq_f2p_mode" value="DIRECT" description="" />
+ <keyValuePair key="pcw_m_axi_gp0_freqmhz" value="50" description="" />
+ <keyValuePair key="pcw_m_axi_gp1_freqmhz" value="10" description="" />
+ <keyValuePair key="pcw_nand_cycles_t_ar" value="1" description="" />
+ <keyValuePair key="pcw_nand_cycles_t_clr" value="1" description="" />
+ <keyValuePair key="pcw_nand_cycles_t_rc" value="11" description="" />
+ <keyValuePair key="pcw_nand_cycles_t_rea" value="1" description="" />
+ <keyValuePair key="pcw_nand_cycles_t_rr" value="1" description="" />
+ <keyValuePair key="pcw_nand_cycles_t_wc" value="11" description="" />
+ <keyValuePair key="pcw_nand_cycles_t_wp" value="1" description="" />
+ <keyValuePair key="pcw_nand_grp_d8_enable" value="0" description="" />
+ <keyValuePair key="pcw_nand_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_nor_cs0_t_ceoe" value="1" description="" />
+ <keyValuePair key="pcw_nor_cs0_t_pc" value="1" description="" />
+ <keyValuePair key="pcw_nor_cs0_t_rc" value="11" description="" />
+ <keyValuePair key="pcw_nor_cs0_t_tr" value="1" description="" />
+ <keyValuePair key="pcw_nor_cs0_t_wc" value="11" description="" />
+ <keyValuePair key="pcw_nor_cs0_t_wp" value="1" description="" />
+ <keyValuePair key="pcw_nor_cs0_we_time" value="0" description="" />
+ <keyValuePair key="pcw_nor_cs1_t_ceoe" value="1" description="" />
+ <keyValuePair key="pcw_nor_cs1_t_pc" value="1" description="" />
+ <keyValuePair key="pcw_nor_cs1_t_rc" value="11" description="" />
+ <keyValuePair key="pcw_nor_cs1_t_tr" value="1" description="" />
+ <keyValuePair key="pcw_nor_cs1_t_wc" value="11" description="" />
+ <keyValuePair key="pcw_nor_cs1_t_wp" value="1" description="" />
+ <keyValuePair key="pcw_nor_cs1_we_time" value="0" description="" />
+ <keyValuePair key="pcw_nor_grp_a25_enable" value="0" description="" />
+ <keyValuePair key="pcw_nor_grp_cs0_enable" value="0" description="" />
+ <keyValuePair key="pcw_nor_grp_cs1_enable" value="0" description="" />
+ <keyValuePair key="pcw_nor_grp_sram_cs0_enable" value="0" description="" />
+ <keyValuePair key="pcw_nor_grp_sram_cs1_enable" value="0" description="" />
+ <keyValuePair key="pcw_nor_grp_sram_int_enable" value="0" description="" />
+ <keyValuePair key="pcw_nor_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_nor_sram_cs0_t_ceoe" value="1" description="" />
+ <keyValuePair key="pcw_nor_sram_cs0_t_pc" value="1" description="" />
+ <keyValuePair key="pcw_nor_sram_cs0_t_rc" value="11" description="" />
+ <keyValuePair key="pcw_nor_sram_cs0_t_tr" value="1" description="" />
+ <keyValuePair key="pcw_nor_sram_cs0_t_wc" value="11" description="" />
+ <keyValuePair key="pcw_nor_sram_cs0_t_wp" value="1" description="" />
+ <keyValuePair key="pcw_nor_sram_cs0_we_time" value="0" description="" />
+ <keyValuePair key="pcw_nor_sram_cs1_t_ceoe" value="1" description="" />
+ <keyValuePair key="pcw_nor_sram_cs1_t_pc" value="1" description="" />
+ <keyValuePair key="pcw_nor_sram_cs1_t_rc" value="11" description="" />
+ <keyValuePair key="pcw_nor_sram_cs1_t_tr" value="1" description="" />
+ <keyValuePair key="pcw_nor_sram_cs1_t_wc" value="11" description="" />
+ <keyValuePair key="pcw_nor_sram_cs1_t_wp" value="1" description="" />
+ <keyValuePair key="pcw_nor_sram_cs1_we_time" value="0" description="" />
+ <keyValuePair key="pcw_override_basic_clock" value="0" description="" />
+ <keyValuePair key="pcw_pcap_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_pcap_peripheral_freqmhz" value="200" description="" />
+ <keyValuePair key="pcw_pjtag_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_preset_bank0_voltage" value="LVCMOS 3.3V" description="" />
+ <keyValuePair key="pcw_preset_bank1_voltage" value="LVCMOS 3.3V" description="" />
+ <keyValuePair key="pcw_qspi_grp_fbclk_enable" value="0" description="" />
+ <keyValuePair key="pcw_qspi_grp_io1_enable" value="0" description="" />
+ <keyValuePair key="pcw_qspi_grp_single_ss_enable" value="0" description="" />
+ <keyValuePair key="pcw_qspi_grp_ss1_enable" value="0" description="" />
+ <keyValuePair key="pcw_qspi_internal_highaddress" value="0xFCFFFFFF" description="" />
+ <keyValuePair key="pcw_qspi_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_qspi_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_qspi_peripheral_freqmhz" value="200" description="" />
+ <keyValuePair key="pcw_s_axi_acp_freqmhz" value="10" description="" />
+ <keyValuePair key="pcw_s_axi_gp0_freqmhz" value="10" description="" />
+ <keyValuePair key="pcw_s_axi_gp1_freqmhz" value="10" description="" />
+ <keyValuePair key="pcw_s_axi_hp0_data_width" value="64" description="" />
+ <keyValuePair key="pcw_s_axi_hp0_freqmhz" value="50" description="" />
+ <keyValuePair key="pcw_s_axi_hp1_data_width" value="64" description="" />
+ <keyValuePair key="pcw_s_axi_hp1_freqmhz" value="10" description="" />
+ <keyValuePair key="pcw_s_axi_hp2_data_width" value="64" description="" />
+ <keyValuePair key="pcw_s_axi_hp2_freqmhz" value="10" description="" />
+ <keyValuePair key="pcw_s_axi_hp3_data_width" value="64" description="" />
+ <keyValuePair key="pcw_s_axi_hp3_freqmhz" value="10" description="" />
+ <keyValuePair key="pcw_sd0_grp_cd_enable" value="0" description="" />
+ <keyValuePair key="pcw_sd0_grp_pow_enable" value="0" description="" />
+ <keyValuePair key="pcw_sd0_grp_wp_enable" value="0" description="" />
+ <keyValuePair key="pcw_sd0_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_sd1_grp_cd_enable" value="0" description="" />
+ <keyValuePair key="pcw_sd1_grp_pow_enable" value="0" description="" />
+ <keyValuePair key="pcw_sd1_grp_wp_enable" value="0" description="" />
+ <keyValuePair key="pcw_sd1_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_sdio_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_sdio_peripheral_freqmhz" value="100" description="" />
+ <keyValuePair key="pcw_smc_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_smc_peripheral_freqmhz" value="100" description="" />
+ <keyValuePair key="pcw_spi0_grp_ss0_enable" value="0" description="" />
+ <keyValuePair key="pcw_spi0_grp_ss1_enable" value="0" description="" />
+ <keyValuePair key="pcw_spi0_grp_ss2_enable" value="0" description="" />
+ <keyValuePair key="pcw_spi0_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_spi1_grp_ss0_enable" value="0" description="" />
+ <keyValuePair key="pcw_spi1_grp_ss1_enable" value="0" description="" />
+ <keyValuePair key="pcw_spi1_grp_ss2_enable" value="0" description="" />
+ <keyValuePair key="pcw_spi1_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_spi_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_spi_peripheral_freqmhz" value="166.666666" description="" />
+ <keyValuePair key="pcw_tpiu_peripheral_clksrc" value="External" description="" />
+ <keyValuePair key="pcw_tpiu_peripheral_freqmhz" value="200" description="" />
+ <keyValuePair key="pcw_trace_grp_16bit_enable" value="0" description="" />
+ <keyValuePair key="pcw_trace_grp_2bit_enable" value="0" description="" />
+ <keyValuePair key="pcw_trace_grp_32bit_enable" value="0" description="" />
+ <keyValuePair key="pcw_trace_grp_4bit_enable" value="0" description="" />
+ <keyValuePair key="pcw_trace_grp_8bit_enable" value="0" description="" />
+ <keyValuePair key="pcw_trace_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_ttc0_clk0_peripheral_clksrc" value="CPU_1X" description="" />
+ <keyValuePair key="pcw_ttc0_clk0_peripheral_freqmhz" value="133.333333" description="" />
+ <keyValuePair key="pcw_ttc0_clk1_peripheral_clksrc" value="CPU_1X" description="" />
+ <keyValuePair key="pcw_ttc0_clk1_peripheral_freqmhz" value="133.333333" description="" />
+ <keyValuePair key="pcw_ttc0_clk2_peripheral_clksrc" value="CPU_1X" description="" />
+ <keyValuePair key="pcw_ttc0_clk2_peripheral_freqmhz" value="133.333333" description="" />
+ <keyValuePair key="pcw_ttc0_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_ttc1_clk0_peripheral_clksrc" value="CPU_1X" description="" />
+ <keyValuePair key="pcw_ttc1_clk0_peripheral_freqmhz" value="133.333333" description="" />
+ <keyValuePair key="pcw_ttc1_clk1_peripheral_clksrc" value="CPU_1X" description="" />
+ <keyValuePair key="pcw_ttc1_clk1_peripheral_freqmhz" value="133.333333" description="" />
+ <keyValuePair key="pcw_ttc1_clk2_peripheral_clksrc" value="CPU_1X" description="" />
+ <keyValuePair key="pcw_ttc1_clk2_peripheral_freqmhz" value="133.333333" description="" />
+ <keyValuePair key="pcw_ttc1_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_ttc_peripheral_freqmhz" value="50" description="" />
+ <keyValuePair key="pcw_uart0_baud_rate" value="115200" description="" />
+ <keyValuePair key="pcw_uart0_grp_full_enable" value="0" description="" />
+ <keyValuePair key="pcw_uart0_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_uart1_baud_rate" value="115200" description="" />
+ <keyValuePair key="pcw_uart1_grp_full_enable" value="0" description="" />
+ <keyValuePair key="pcw_uart1_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_uart_peripheral_clksrc" value="IO PLL" description="" />
+ <keyValuePair key="pcw_uart_peripheral_freqmhz" value="100" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_adv_enable" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_al" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_bank_addr_count" value="3" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_bl" value="8" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_board_delay0" value="0.25" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_board_delay1" value="0.25" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_board_delay2" value="0.25" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_board_delay3" value="0.25" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_bus_width" value="32 Bit" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_cl" value="7" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_0_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_0_package_length" value="80.4535" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_0_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_1_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_1_package_length" value="80.4535" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_1_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_2_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_2_package_length" value="80.4535" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_2_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_3_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_3_package_length" value="80.4535" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_3_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_clock_stop_en" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_col_addr_count" value="10" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_cwl" value="6" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_device_capacity" value="1024 MBits" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_0_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_0_package_length" value="98.503" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_0_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_1_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_1_package_length" value="68.5855" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_1_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_2_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_2_package_length" value="90.295" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_2_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_3_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_3_package_length" value="103.977" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dq_3_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_0_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_0_package_length" value="105.056" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_0_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_1_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_1_package_length" value="66.904" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_1_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_2_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_2_package_length" value="89.1715" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_2_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_3_length_mm" value="0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_3_package_length" value="113.63" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_3_propogation_delay" value="160" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_to_clk_delay_0" value="0.0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_to_clk_delay_1" value="0.0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_to_clk_delay_2" value="0.0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dqs_to_clk_delay_3" value="0.0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_dram_width" value="8 Bits" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_ecc" value="Disabled" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_enable" value="1" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_freq_mhz" value="533.333333" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_high_temp" value="Normal (0-85)" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_memory_type" value="DDR 3" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_partno" value="MT41J128M8 JP-125" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_row_addr_count" value="14" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_speed_bin" value="DDR3_1066F" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_t_faw" value="30.0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_t_ras_min" value="35.0" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_t_rc" value="48.75" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_t_rcd" value="7" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_t_rp" value="7" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_train_data_eye" value="1" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_train_read_gate" value="1" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_train_write_level" value="1" description="" />
+ <keyValuePair key="pcw_uiparam_ddr_use_internal_vref" value="0" description="" />
+ <keyValuePair key="pcw_usb0_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_usb0_peripheral_freqmhz" value="60" description="" />
+ <keyValuePair key="pcw_usb0_reset_enable" value="0" description="" />
+ <keyValuePair key="pcw_usb1_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_usb1_peripheral_freqmhz" value="60" description="" />
+ <keyValuePair key="pcw_usb1_reset_enable" value="0" description="" />
+ <keyValuePair key="pcw_usb_reset_polarity" value="Active Low" description="" />
+ <keyValuePair key="pcw_use_cross_trigger" value="0" description="" />
+ <keyValuePair key="pcw_use_m_axi_gp0" value="1" description="" />
+ <keyValuePair key="pcw_use_m_axi_gp1" value="0" description="" />
+ <keyValuePair key="pcw_use_s_axi_acp" value="0" description="" />
+ <keyValuePair key="pcw_use_s_axi_gp0" value="0" description="" />
+ <keyValuePair key="pcw_use_s_axi_gp1" value="0" description="" />
+ <keyValuePair key="pcw_use_s_axi_hp0" value="1" description="" />
+ <keyValuePair key="pcw_use_s_axi_hp1" value="0" description="" />
+ <keyValuePair key="pcw_use_s_axi_hp2" value="0" description="" />
+ <keyValuePair key="pcw_use_s_axi_hp3" value="0" description="" />
+ <keyValuePair key="pcw_wdt_peripheral_clksrc" value="CPU_1X" description="" />
+ <keyValuePair key="pcw_wdt_peripheral_enable" value="0" description="" />
+ <keyValuePair key="pcw_wdt_peripheral_freqmhz" value="133.333333" description="" />
+ </section>
+ <section name="processing_system7_v5_5_processing_system7/1" level="2" order="13" description="">
+ <keyValuePair key="c_dm_width" value="4" description="" />
+ <keyValuePair key="c_dq_width" value="32" description="" />
+ <keyValuePair key="c_dqs_width" value="4" description="" />
+ <keyValuePair key="c_emio_gpio_width" value="64" description="" />
+ <keyValuePair key="c_en_emio_enet0" value="0" description="" />
+ <keyValuePair key="c_en_emio_enet1" value="0" description="" />
+ <keyValuePair key="c_en_emio_pjtag" value="0" description="" />
+ <keyValuePair key="c_en_emio_trace" value="0" description="" />
+ <keyValuePair key="c_fclk_clk0_buf" value="TRUE" description="" />
+ <keyValuePair key="c_fclk_clk1_buf" value="FALSE" description="" />
+ <keyValuePair key="c_fclk_clk2_buf" value="FALSE" description="" />
+ <keyValuePair key="c_fclk_clk3_buf" value="FALSE" description="" />
+ <keyValuePair key="c_gp0_en_modifiable_txn" value="1" description="" />
+ <keyValuePair key="c_gp1_en_modifiable_txn" value="1" description="" />
+ <keyValuePair key="c_include_acp_trans_check" value="0" description="" />
+ <keyValuePair key="c_include_trace_buffer" value="0" description="" />
+ <keyValuePair key="c_irq_f2p_mode" value="DIRECT" description="" />
+ <keyValuePair key="c_m_axi_gp0_enable_static_remap" value="0" description="" />
+ <keyValuePair key="c_m_axi_gp0_id_width" value="12" description="" />
+ <keyValuePair key="c_m_axi_gp0_thread_id_width" value="12" description="" />
+ <keyValuePair key="c_m_axi_gp1_enable_static_remap" value="0" description="" />
+ <keyValuePair key="c_m_axi_gp1_id_width" value="12" description="" />
+ <keyValuePair key="c_m_axi_gp1_thread_id_width" value="12" description="" />
+ <keyValuePair key="c_mio_primitive" value="54" description="" />
+ <keyValuePair key="c_num_f2p_intr_inputs" value="1" description="" />
+ <keyValuePair key="c_package_name" value="clg400" description="" />
+ <keyValuePair key="c_ps7_si_rev" value="PRODUCTION" description="" />
+ <keyValuePair key="c_s_axi_acp_aruser_val" value="31" description="" />
+ <keyValuePair key="c_s_axi_acp_awuser_val" value="31" description="" />
+ <keyValuePair key="c_s_axi_acp_id_width" value="3" description="" />
+ <keyValuePair key="c_s_axi_gp0_id_width" value="6" description="" />
+ <keyValuePair key="c_s_axi_gp1_id_width" value="6" description="" />
+ <keyValuePair key="c_s_axi_hp0_data_width" value="64" description="" />
+ <keyValuePair key="c_s_axi_hp0_id_width" value="6" description="" />
+ <keyValuePair key="c_s_axi_hp1_data_width" value="64" description="" />
+ <keyValuePair key="c_s_axi_hp1_id_width" value="6" description="" />
+ <keyValuePair key="c_s_axi_hp2_data_width" value="64" description="" />
+ <keyValuePair key="c_s_axi_hp2_id_width" value="6" description="" />
+ <keyValuePair key="c_s_axi_hp3_data_width" value="64" description="" />
+ <keyValuePair key="c_s_axi_hp3_id_width" value="6" description="" />
+ <keyValuePair key="c_trace_buffer_clock_delay" value="12" description="" />
+ <keyValuePair key="c_trace_buffer_fifo_size" value="128" description="" />
+ <keyValuePair key="c_trace_internal_width" value="2" description="" />
+ <keyValuePair key="c_trace_pipeline_width" value="8" description="" />
+ <keyValuePair key="c_use_axi_nonsecure" value="0" description="" />
+ <keyValuePair key="c_use_default_acp_user_val" value="0" description="" />
+ <keyValuePair key="c_use_m_axi_gp0" value="1" description="" />
+ <keyValuePair key="c_use_m_axi_gp1" value="0" description="" />
+ <keyValuePair key="c_use_s_axi_acp" value="0" description="" />
+ <keyValuePair key="c_use_s_axi_gp0" value="0" description="" />
+ <keyValuePair key="c_use_s_axi_gp1" value="0" description="" />
+ <keyValuePair key="c_use_s_axi_hp0" value="1" description="" />
+ <keyValuePair key="c_use_s_axi_hp1" value="0" description="" />
+ <keyValuePair key="c_use_s_axi_hp2" value="0" description="" />
+ <keyValuePair key="c_use_s_axi_hp3" value="0" description="" />
+ <keyValuePair key="core_container" value="NA" description="" />
+ <keyValuePair key="iptotal" value="1" description="" />
+ <keyValuePair key="use_trace_data_edge_detector" value="0" description="" />
+ <keyValuePair key="x_ipcorerevision" value="6" description="" />
+ <keyValuePair key="x_iplanguage" value="VERILOG" description="" />
+ <keyValuePair key="x_iplibrary" value="ip" description="" />
+ <keyValuePair key="x_ipname" value="processing_system7" description="" />
+ <keyValuePair key="x_ipproduct" value="Vivado 2020.2" description="" />
+ <keyValuePair key="x_ipsimlanguage" value="MIXED" description="" />
+ <keyValuePair key="x_ipvendor" value="xilinx.com" description="" />
+ <keyValuePair key="x_ipversion" value="5.5" description="" />
+ </section>
+ <section name="xpm_cdc_async_rst/1" level="2" order="14" description="">
+ <keyValuePair key="core_container" value="NA" description="" />
+ <keyValuePair key="def_val" value="1'b0" description="" />
+ <keyValuePair key="dest_sync_ff" value="2" description="" />
+ <keyValuePair key="init_sync_ff" value="0" description="" />
+ <keyValuePair key="inv_def_val" value="1'b1" description="" />
+ <keyValuePair key="iptotal" value="3" description="" />
+ <keyValuePair key="rst_active_high" value="1" description="" />
+ <keyValuePair key="version" value="0" description="" />
+ </section>
+ <section name="xpm_fifo_base/1" level="2" order="15" description="">
+ <keyValuePair key="both_stages_valid" value="3" description="" />
+ <keyValuePair key="cascade_height" value="0" description="" />
+ <keyValuePair key="cdc_dest_sync_ff" value="2" description="" />
+ <keyValuePair key="common_clock" value="1" description="" />
+ <keyValuePair key="core_container" value="NA" description="" />
+ <keyValuePair key="dout_reset_value" value="0" description="" />
+ <keyValuePair key="ecc_mode" value="0" description="" />
+ <keyValuePair key="en_adv_feature" value="16'b0001111100011111" description="" />
+ <keyValuePair key="en_ae" value="1'b1" description="" />
+ <keyValuePair key="en_af" value="1'b1" description="" />
+ <keyValuePair key="en_dvld" value="1'b1" description="" />
+ <keyValuePair key="en_of" value="1'b1" description="" />
+ <keyValuePair key="en_pe" value="1'b1" description="" />
+ <keyValuePair key="en_pf" value="1'b1" description="" />
+ <keyValuePair key="en_rdc" value="1'b1" description="" />
+ <keyValuePair key="en_uf" value="1'b1" description="" />
+ <keyValuePair key="en_wack" value="1'b1" description="" />
+ <keyValuePair key="en_wdc" value="1'b1" description="" />
+ <keyValuePair key="enable_ecc" value="0" description="" />
+ <keyValuePair key="fg_eq_asym_dout" value="1'b0" description="" />
+ <keyValuePair key="fifo_mem_type" value="0" description="" />
+ <keyValuePair key="fifo_memory_type" value="0" description="" />
+ <keyValuePair key="fifo_read_depth" value="16" description="" />
+ <keyValuePair key="fifo_read_latency" value="0" description="" />
+ <keyValuePair key="fifo_size" value="144" description="" />
+ <keyValuePair key="fifo_write_depth" value="16" description="" />
+ <keyValuePair key="full_reset_value" value="1" description="" />
+ <keyValuePair key="full_rst_val" value="1'b1" description="" />
+ <keyValuePair key="invalid" value="0" description="" />
+ <keyValuePair key="iptotal" value="3" description="" />
+ <keyValuePair key="pe_thresh_adj" value="8" description="" />
+ <keyValuePair key="pe_thresh_max" value="11" description="" />
+ <keyValuePair key="pe_thresh_min" value="5" description="" />
+ <keyValuePair key="pf_thresh_adj" value="8" description="" />
+ <keyValuePair key="pf_thresh_max" value="11" description="" />
+ <keyValuePair key="pf_thresh_min" value="5" description="" />
+ <keyValuePair key="prog_empty_thresh" value="10" description="" />
+ <keyValuePair key="prog_full_thresh" value="10" description="" />
+ <keyValuePair key="rd_data_count_width" value="4" description="" />
+ <keyValuePair key="rd_dc_width_ext" value="5" description="" />
+ <keyValuePair key="rd_latency" value="2" description="" />
+ <keyValuePair key="rd_mode" value="1" description="" />
+ <keyValuePair key="rd_pntr_width" value="4" description="" />
+ <keyValuePair key="read_data_width" value="9" description="" />
+ <keyValuePair key="read_mode" value="1" description="" />
+ <keyValuePair key="read_mode_ll" value="1" description="" />
+ <keyValuePair key="related_clocks" value="0" description="" />
+ <keyValuePair key="remove_wr_rd_prot_logic" value="0" description="" />
+ <keyValuePair key="sim_assert_chk" value="0" description="" />
+ <keyValuePair key="stage1_valid" value="2" description="" />
+ <keyValuePair key="stage2_valid" value="1" description="" />
+ <keyValuePair key="use_adv_features" value="1F1F" description="" />
+ <keyValuePair key="version" value="0" description="" />
+ <keyValuePair key="wakeup_time" value="0" description="" />
+ <keyValuePair key="width_ratio" value="1" description="" />
+ <keyValuePair key="wr_data_count_width" value="5" description="" />
+ <keyValuePair key="wr_dc_width_ext" value="5" description="" />
+ <keyValuePair key="wr_depth_log" value="4" description="" />
+ <keyValuePair key="wr_pntr_width" value="4" description="" />
+ <keyValuePair key="wr_rd_ratio" value="0" description="" />
+ <keyValuePair key="wr_width_log" value="4" description="" />
+ <keyValuePair key="write_data_width" value="9" description="" />
+ </section>
+ <section name="xpm_fifo_sync/1" level="2" order="16" description="">
+ <keyValuePair key="cascade_height" value="0" description="" />
+ <keyValuePair key="core_container" value="NA" description="" />
+ <keyValuePair key="dout_reset_value" value="0" description="" />
+ <keyValuePair key="ecc_mode" value="no_ecc" description="" />
+ <keyValuePair key="en_adv_feature_sync" value="16'b0001111100011111" description="" />
+ <keyValuePair key="fifo_memory_type" value="auto" description="" />
+ <keyValuePair key="fifo_read_latency" value="0" description="" />
+ <keyValuePair key="fifo_write_depth" value="16" description="" />
+ <keyValuePair key="full_reset_value" value="1" description="" />
+ <keyValuePair key="iptotal" value="3" description="" />
+ <keyValuePair key="p_common_clock" value="1" description="" />
+ <keyValuePair key="p_ecc_mode" value="0" description="" />
+ <keyValuePair key="p_fifo_memory_type" value="0" description="" />
+ <keyValuePair key="p_read_mode" value="1" description="" />
+ <keyValuePair key="p_wakeup_time" value="2" description="" />
+ <keyValuePair key="prog_empty_thresh" value="10" description="" />
+ <keyValuePair key="prog_full_thresh" value="10" description="" />
+ <keyValuePair key="rd_data_count_width" value="4" description="" />
+ <keyValuePair key="read_data_width" value="9" description="" />
+ <keyValuePair key="read_mode" value="fwft" description="" />
+ <keyValuePair key="sim_assert_chk" value="0" description="" />
+ <keyValuePair key="use_adv_features" value="1F1F" description="" />
+ <keyValuePair key="wakeup_time" value="0" description="" />
+ <keyValuePair key="wr_data_count_width" value="5" description="" />
+ <keyValuePair key="write_data_width" value="9" description="" />
+ </section>
+ <section name="xpm_memory_base/1" level="2" order="17" description="">
+ <keyValuePair key="addr_width_a" value="4" description="" />
+ <keyValuePair key="addr_width_b" value="4" description="" />
+ <keyValuePair key="auto_sleep_time" value="0" description="" />
+ <keyValuePair key="byte_write_width_a" value="9" description="" />
+ <keyValuePair key="byte_write_width_b" value="9" description="" />
+ <keyValuePair key="cascade_height" value="0" description="" />
+ <keyValuePair key="clocking_mode" value="0" description="" />
+ <keyValuePair key="core_container" value="NA" description="" />
+ <keyValuePair key="ecc_mode" value="0" description="" />
+ <keyValuePair key="iptotal" value="3" description="" />
+ <keyValuePair key="max_num_char" value="0" description="" />
+ <keyValuePair key="memory_optimization" value="true" description="" />
+ <keyValuePair key="memory_primitive" value="0" description="" />
+ <keyValuePair key="memory_size" value="144" description="" />
+ <keyValuePair key="memory_type" value="1" description="" />
+ <keyValuePair key="message_control" value="0" description="" />
+ <keyValuePair key="num_char_loc" value="0" description="" />
+ <keyValuePair key="p_ecc_mode" value="no_ecc" description="" />
+ <keyValuePair key="p_enable_byte_write_a" value="0" description="" />
+ <keyValuePair key="p_enable_byte_write_b" value="0" description="" />
+ <keyValuePair key="p_max_depth_data" value="16" description="" />
+ <keyValuePair key="p_memory_opt" value="yes" description="" />
+ <keyValuePair key="p_memory_primitive" value="auto" description="" />
+ <keyValuePair key="p_min_width_data" value="9" description="" />
+ <keyValuePair key="p_min_width_data_a" value="9" description="" />
+ <keyValuePair key="p_min_width_data_b" value="9" description="" />
+ <keyValuePair key="p_min_width_data_ecc" value="9" description="" />
+ <keyValuePair key="p_min_width_data_ldw" value="4" description="" />
+ <keyValuePair key="p_min_width_data_shft" value="9" description="" />
+ <keyValuePair key="p_num_cols_write_a" value="1" description="" />
+ <keyValuePair key="p_num_cols_write_b" value="1" description="" />
+ <keyValuePair key="p_num_rows_read_a" value="1" description="" />
+ <keyValuePair key="p_num_rows_read_b" value="1" description="" />
+ <keyValuePair key="p_num_rows_write_a" value="1" description="" />
+ <keyValuePair key="p_num_rows_write_b" value="1" description="" />
+ <keyValuePair key="p_sdp_write_mode" value="yes" description="" />
+ <keyValuePair key="p_width_addr_lsb_read_a" value="0" description="" />
+ <keyValuePair key="p_width_addr_lsb_read_b" value="0" description="" />
+ <keyValuePair key="p_width_addr_lsb_write_a" value="0" description="" />
+ <keyValuePair key="p_width_addr_lsb_write_b" value="0" description="" />
+ <keyValuePair key="p_width_addr_read_a" value="4" description="" />
+ <keyValuePair key="p_width_addr_read_b" value="4" description="" />
+ <keyValuePair key="p_width_addr_write_a" value="4" description="" />
+ <keyValuePair key="p_width_addr_write_b" value="4" description="" />
+ <keyValuePair key="p_width_col_write_a" value="9" description="" />
+ <keyValuePair key="p_width_col_write_b" value="9" description="" />
+ <keyValuePair key="read_data_width_a" value="9" description="" />
+ <keyValuePair key="read_data_width_b" value="9" description="" />
+ <keyValuePair key="read_latency_a" value="2" description="" />
+ <keyValuePair key="read_latency_b" value="2" description="" />
+ <keyValuePair key="read_reset_value_a" value="0" description="" />
+ <keyValuePair key="read_reset_value_b" value="0" description="" />
+ <keyValuePair key="rst_mode_a" value="SYNC" description="" />
+ <keyValuePair key="rst_mode_b" value="SYNC" description="" />
+ <keyValuePair key="rsta_loop_iter" value="12" description="" />
+ <keyValuePair key="rstb_loop_iter" value="12" description="" />
+ <keyValuePair key="sim_assert_chk" value="0" description="" />
+ <keyValuePair key="use_embedded_constraint" value="0" description="" />
+ <keyValuePair key="use_mem_init" value="0" description="" />
+ <keyValuePair key="use_mem_init_mmi" value="0" description="" />
+ <keyValuePair key="version" value="0" description="" />
+ <keyValuePair key="wakeup_time" value="0" description="" />
+ <keyValuePair key="write_data_width" value="9" description="" />
+ <keyValuePair key="write_data_width_a" value="9" description="" />
+ <keyValuePair key="write_data_width_b" value="9" description="" />
+ <keyValuePair key="write_mode_a" value="2" description="" />
+ <keyValuePair key="write_mode_b" value="2" description="" />
+ <keyValuePair key="write_protect" value="1" description="" />
+ </section>
+ </section>
+ <section name="phys_opt_design_post_place" level="1" order="4" description="">
+ <section name="command_line_options" level="2" order="1" description="">
+ <keyValuePair key="-aggressive_hold_fix" value="default::[not_specified]" description="" />
+ <keyValuePair key="-bram_register_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-clock_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-critical_cell_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-critical_pin_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-directive" value="default::[not_specified]" description="" />
+ <keyValuePair key="-dsp_register_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-effort_level" value="default::[not_specified]" description="" />
+ <keyValuePair key="-fanout_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-hold_fix" value="default::[not_specified]" description="" />
+ <keyValuePair key="-insert_negative_edge_ffs" value="default::[not_specified]" description="" />
+ <keyValuePair key="-multi_clock_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-placement_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-restruct_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-retime" value="default::[not_specified]" description="" />
+ <keyValuePair key="-rewire" value="default::[not_specified]" description="" />
+ <keyValuePair key="-shift_register_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-uram_register_opt" value="default::[not_specified]" description="" />
+ <keyValuePair key="-verbose" value="default::[not_specified]" description="" />
+ <keyValuePair key="-vhfn" value="default::[not_specified]" description="" />
+ </section>
+ </section>
+ <section name="power_opt_design" level="1" order="5" description="">
+ <section name="command_line_options_spo" level="2" order="1" description="">
+ <keyValuePair key="-cell_types" value="default::all" description="" />
+ <keyValuePair key="-clocks" value="default::[not_specified]" description="" />
+ <keyValuePair key="-exclude_cells" value="default::[not_specified]" description="" />
+ <keyValuePair key="-include_cells" value="default::[not_specified]" description="" />
+ </section>
+ <section name="usage" level="2" order="2" description="">
+ <keyValuePair key="bram_ports_augmented" value="3" description="" />
+ <keyValuePair key="bram_ports_newly_gated" value="0" description="" />
+ <keyValuePair key="bram_ports_total" value="4" description="" />
+ <keyValuePair key="flow_state" value="default" description="" />
+ <keyValuePair key="slice_registers_augmented" value="0" description="" />
+ <keyValuePair key="slice_registers_newly_gated" value="0" description="" />
+ <keyValuePair key="slice_registers_total" value="4075" description="" />
+ <keyValuePair key="srls_augmented" value="0" description="" />
+ <keyValuePair key="srls_newly_gated" value="0" description="" />
+ <keyValuePair key="srls_total" value="285" description="" />
+ </section>
+ </section>
+ <section name="report_drc" level="1" order="6" description="">
+ <section name="command_line_options" level="2" order="1" description="">
+ <keyValuePair key="-append" value="default::[not_specified]" description="" />
+ <keyValuePair key="-checks" value="default::[not_specified]" description="" />
+ <keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
+ <keyValuePair key="-force" value="default::[not_specified]" description="" />
+ <keyValuePair key="-format" value="default::[not_specified]" description="" />
+ <keyValuePair key="-internal" value="default::[not_specified]" description="" />
+ <keyValuePair key="-internal_only" value="default::[not_specified]" description="" />
+ <keyValuePair key="-max_msgs_per_check" value="default::[not_specified]" description="" />
+ <keyValuePair key="-messages" value="default::[not_specified]" description="" />
+ <keyValuePair key="-name" value="default::[not_specified]" description="" />
+ <keyValuePair key="-no_waivers" value="default::[not_specified]" description="" />
+ <keyValuePair key="-return_string" value="default::[not_specified]" description="" />
+ <keyValuePair key="-ruledecks" value="default::[not_specified]" description="" />
+ <keyValuePair key="-upgrade_cw" value="default::[not_specified]" description="" />
+ <keyValuePair key="-waived" value="default::[not_specified]" description="" />
+ </section>
+ <section name="results" level="2" order="2" description="">
+ <keyValuePair key="reqp-181" value="2" description="" />
+ <keyValuePair key="rtstat-10" value="1" description="" />
+ </section>
+ </section>
+ <section name="report_methodology" level="1" order="7" description="">
+ <section name="command_line_options" level="2" order="1" description="">
+ <keyValuePair key="-append" value="default::[not_specified]" description="" />
+ <keyValuePair key="-checks" value="default::[not_specified]" description="" />
+ <keyValuePair key="-fail_on" value="default::[not_specified]" description="" />
+ <keyValuePair key="-force" value="default::[not_specified]" description="" />
+ <keyValuePair key="-format" value="default::[not_specified]" description="" />
+ <keyValuePair key="-messages" value="default::[not_specified]" description="" />
+ <keyValuePair key="-name" value="default::[not_specified]" description="" />
+ <keyValuePair key="-return_string" value="default::[not_specified]" description="" />
+ <keyValuePair key="-slack_lesser_than" value="default::[not_specified]" description="" />
+ <keyValuePair key="-waived" value="default::[not_specified]" description="" />
+ </section>
+ <section name="results" level="2" order="2" description="">
+ <keyValuePair key="lutar-1" value="3" description="" />
+ </section>
+ </section>
+ <section name="report_power" level="1" order="8" description="">
+ <section name="command_line_options" level="2" order="1" description="">
+ <keyValuePair key="-advisory" value="default::[not_specified]" description="" />
+ <keyValuePair key="-append" value="default::[not_specified]" description="" />
+ <keyValuePair key="-file" value="[specified]" description="" />
+ <keyValuePair key="-format" value="default::text" description="" />
+ <keyValuePair key="-hier" value="default::power" description="" />
+ <keyValuePair key="-hierarchical_depth" value="default::4" description="" />
+ <keyValuePair key="-l" value="default::[not_specified]" description="" />
+ <keyValuePair key="-name" value="default::[not_specified]" description="" />
+ <keyValuePair key="-no_propagation" value="default::[not_specified]" description="" />
+ <keyValuePair key="-return_string" value="default::[not_specified]" description="" />
+ <keyValuePair key="-rpx" value="[specified]" description="" />
+ <keyValuePair key="-verbose" value="default::[not_specified]" description="" />
+ <keyValuePair key="-vid" value="default::[not_specified]" description="" />
+ <keyValuePair key="-xpe" value="default::[not_specified]" description="" />
+ </section>
+ <section name="usage" level="2" order="2" description="">
+ <keyValuePair key="airflow" value="250 (LFM)" description="" />
+ <keyValuePair key="ambient_temp" value="25.0 (C)" description="" />
+ <keyValuePair key="bi-dir_toggle" value="12.500000" description="" />
+ <keyValuePair key="bidir_output_enable" value="1.000000" description="" />
+ <keyValuePair key="board_layers" value="8to11 (8 to 11 Layers)" description="" />
+ <keyValuePair key="board_selection" value="medium (10"x10")" description="" />
+ <keyValuePair key="bram" value="0.000048" description="" />
+ <keyValuePair key="clocks" value="0.007783" description="" />
+ <keyValuePair key="confidence_level_clock_activity" value="High" description="" />
+ <keyValuePair key="confidence_level_design_state" value="High" description="" />
+ <keyValuePair key="confidence_level_device_models" value="High" description="" />
+ <keyValuePair key="confidence_level_internal_activity" value="Medium" description="" />
+ <keyValuePair key="confidence_level_io_activity" value="High" description="" />
+ <keyValuePair key="confidence_level_overall" value="Medium" description="" />
+ <keyValuePair key="customer" value="TBD" description="" />
+ <keyValuePair key="customer_class" value="TBD" description="" />
+ <keyValuePair key="devstatic" value="0.136176" description="" />
+ <keyValuePair key="die" value="xc7z020clg400-1" description="" />
+ <keyValuePair key="dsp_output_toggle" value="12.500000" description="" />
+ <keyValuePair key="dynamic" value="1.537895" description="" />
+ <keyValuePair key="effective_thetaja" value="11.53" description="" />
+ <keyValuePair key="enable_probability" value="0.990000" description="" />
+ <keyValuePair key="family" value="zynq" description="" />
+ <keyValuePair key="ff_toggle" value="12.500000" description="" />
+ <keyValuePair key="flow_state" value="routed" description="" />
+ <keyValuePair key="heatsink" value="none" description="" />
+ <keyValuePair key="input_toggle" value="12.500000" description="" />
+ <keyValuePair key="junction_temp" value="44.3 (C)" description="" />
+ <keyValuePair key="logic" value="0.001146" description="" />
+ <keyValuePair key="mgtavcc_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="mgtavcc_static_current" value="0.000000" description="" />
+ <keyValuePair key="mgtavcc_total_current" value="0.000000" description="" />
+ <keyValuePair key="mgtavcc_voltage" value="1.000000" description="" />
+ <keyValuePair key="mgtavtt_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="mgtavtt_static_current" value="0.000000" description="" />
+ <keyValuePair key="mgtavtt_total_current" value="0.000000" description="" />
+ <keyValuePair key="mgtavtt_voltage" value="1.200000" description="" />
+ <keyValuePair key="mgtvccaux_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="mgtvccaux_static_current" value="0.000000" description="" />
+ <keyValuePair key="mgtvccaux_total_current" value="0.000000" description="" />
+ <keyValuePair key="mgtvccaux_voltage" value="1.800000" description="" />
+ <keyValuePair key="netlist_net_matched" value="NA" description="" />
+ <keyValuePair key="off-chip_power" value="0.000000" description="" />
+ <keyValuePair key="on-chip_power" value="1.674070" description="" />
+ <keyValuePair key="output_enable" value="1.000000" description="" />
+ <keyValuePair key="output_load" value="5.000000" description="" />
+ <keyValuePair key="output_toggle" value="12.500000" description="" />
+ <keyValuePair key="package" value="clg400" description="" />
+ <keyValuePair key="pct_clock_constrained" value="6.480000" description="" />
+ <keyValuePair key="pct_inputs_defined" value="0" description="" />
+ <keyValuePair key="platform" value="lin64" description="" />
+ <keyValuePair key="process" value="typical" description="" />
+ <keyValuePair key="ps7" value="1.527332" description="" />
+ <keyValuePair key="ram_enable" value="50.000000" description="" />
+ <keyValuePair key="ram_write" value="50.000000" description="" />
+ <keyValuePair key="read_saif" value="False" description="" />
+ <keyValuePair key="set/reset_probability" value="0.000000" description="" />
+ <keyValuePair key="signal_rate" value="False" description="" />
+ <keyValuePair key="signals" value="0.001586" description="" />
+ <keyValuePair key="simulation_file" value="None" description="" />
+ <keyValuePair key="speedgrade" value="-1" description="" />
+ <keyValuePair key="static_prob" value="False" description="" />
+ <keyValuePair key="temp_grade" value="commercial" description="" />
+ <keyValuePair key="thetajb" value="7.4 (C/W)" description="" />
+ <keyValuePair key="thetasa" value="0.0 (C/W)" description="" />
+ <keyValuePair key="toggle_rate" value="False" description="" />
+ <keyValuePair key="user_board_temp" value="25.0 (C)" description="" />
+ <keyValuePair key="user_effective_thetaja" value="11.53" description="" />
+ <keyValuePair key="user_junc_temp" value="44.3 (C)" description="" />
+ <keyValuePair key="user_thetajb" value="7.4 (C/W)" description="" />
+ <keyValuePair key="user_thetasa" value="0.0 (C/W)" description="" />
+ <keyValuePair key="vccadc_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vccadc_static_current" value="0.020000" description="" />
+ <keyValuePair key="vccadc_total_current" value="0.020000" description="" />
+ <keyValuePair key="vccadc_voltage" value="1.800000" description="" />
+ <keyValuePair key="vccaux_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vccaux_io_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vccaux_io_static_current" value="0.000000" description="" />
+ <keyValuePair key="vccaux_io_total_current" value="0.000000" description="" />
+ <keyValuePair key="vccaux_io_voltage" value="1.800000" description="" />
+ <keyValuePair key="vccaux_static_current" value="0.015149" description="" />
+ <keyValuePair key="vccaux_total_current" value="0.015149" description="" />
+ <keyValuePair key="vccaux_voltage" value="1.800000" description="" />
+ <keyValuePair key="vccbram_dynamic_current" value="0.000001" description="" />
+ <keyValuePair key="vccbram_static_current" value="0.001026" description="" />
+ <keyValuePair key="vccbram_total_current" value="0.001027" description="" />
+ <keyValuePair key="vccbram_voltage" value="1.000000" description="" />
+ <keyValuePair key="vccint_dynamic_current" value="0.010561" description="" />
+ <keyValuePair key="vccint_static_current" value="0.014849" description="" />
+ <keyValuePair key="vccint_total_current" value="0.025411" description="" />
+ <keyValuePair key="vccint_voltage" value="1.000000" description="" />
+ <keyValuePair key="vcco12_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vcco12_static_current" value="0.000000" description="" />
+ <keyValuePair key="vcco12_total_current" value="0.000000" description="" />
+ <keyValuePair key="vcco12_voltage" value="1.200000" description="" />
+ <keyValuePair key="vcco135_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vcco135_static_current" value="0.000000" description="" />
+ <keyValuePair key="vcco135_total_current" value="0.000000" description="" />
+ <keyValuePair key="vcco135_voltage" value="1.350000" description="" />
+ <keyValuePair key="vcco15_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vcco15_static_current" value="0.000000" description="" />
+ <keyValuePair key="vcco15_total_current" value="0.000000" description="" />
+ <keyValuePair key="vcco15_voltage" value="1.500000" description="" />
+ <keyValuePair key="vcco18_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vcco18_static_current" value="0.000000" description="" />
+ <keyValuePair key="vcco18_total_current" value="0.000000" description="" />
+ <keyValuePair key="vcco18_voltage" value="1.800000" description="" />
+ <keyValuePair key="vcco25_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vcco25_static_current" value="0.000000" description="" />
+ <keyValuePair key="vcco25_total_current" value="0.000000" description="" />
+ <keyValuePair key="vcco25_voltage" value="2.500000" description="" />
+ <keyValuePair key="vcco33_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vcco33_static_current" value="0.000000" description="" />
+ <keyValuePair key="vcco33_total_current" value="0.000000" description="" />
+ <keyValuePair key="vcco33_voltage" value="3.300000" description="" />
+ <keyValuePair key="vcco_ddr_dynamic_current" value="0.456904" description="" />
+ <keyValuePair key="vcco_ddr_static_current" value="0.002000" description="" />
+ <keyValuePair key="vcco_ddr_total_current" value="0.458904" description="" />
+ <keyValuePair key="vcco_ddr_voltage" value="1.500000" description="" />
+ <keyValuePair key="vcco_mio0_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vcco_mio0_static_current" value="0.000000" description="" />
+ <keyValuePair key="vcco_mio0_total_current" value="0.000000" description="" />
+ <keyValuePair key="vcco_mio0_voltage" value="1.800000" description="" />
+ <keyValuePair key="vcco_mio1_dynamic_current" value="0.000000" description="" />
+ <keyValuePair key="vcco_mio1_static_current" value="0.000000" description="" />
+ <keyValuePair key="vcco_mio1_total_current" value="0.000000" description="" />
+ <keyValuePair key="vcco_mio1_voltage" value="1.800000" description="" />
+ <keyValuePair key="vccpaux_dynamic_current" value="0.050131" description="" />
+ <keyValuePair key="vccpaux_static_current" value="0.010330" description="" />
+ <keyValuePair key="vccpaux_total_current" value="0.060461" description="" />
+ <keyValuePair key="vccpaux_voltage" value="1.800000" description="" />
+ <keyValuePair key="vccpint_dynamic_current" value="0.723985" description="" />
+ <keyValuePair key="vccpint_static_current" value="0.030037" description="" />
+ <keyValuePair key="vccpint_total_current" value="0.754023" description="" />
+ <keyValuePair key="vccpint_voltage" value="1.000000" description="" />
+ <keyValuePair key="vccpll_dynamic_current" value="0.015420" description="" />
+ <keyValuePair key="vccpll_static_current" value="0.003000" description="" />
+ <keyValuePair key="vccpll_total_current" value="0.018420" description="" />
+ <keyValuePair key="vccpll_voltage" value="1.800000" description="" />
+ <keyValuePair key="version" value="2020.2" description="" />
+ </section>
+ </section>
+ <section name="report_utilization" level="1" order="9" description="">
+ <section name="clocking" level="2" order="1" description="">
+ <keyValuePair key="bufgctrl_available" value="32" description="" />
+ <keyValuePair key="bufgctrl_fixed" value="0" description="" />
+ <keyValuePair key="bufgctrl_used" value="1" description="" />
+ <keyValuePair key="bufgctrl_util_percentage" value="3.13" description="" />
+ <keyValuePair key="bufhce_available" value="72" description="" />
+ <keyValuePair key="bufhce_fixed" value="0" description="" />
+ <keyValuePair key="bufhce_used" value="0" description="" />
+ <keyValuePair key="bufhce_util_percentage" value="0.00" description="" />
+ <keyValuePair key="bufio_available" value="16" description="" />
+ <keyValuePair key="bufio_fixed" value="0" description="" />
+ <keyValuePair key="bufio_used" value="0" description="" />
+ <keyValuePair key="bufio_util_percentage" value="0.00" description="" />
+ <keyValuePair key="bufmrce_available" value="8" description="" />
+ <keyValuePair key="bufmrce_fixed" value="0" description="" />
+ <keyValuePair key="bufmrce_used" value="0" description="" />
+ <keyValuePair key="bufmrce_util_percentage" value="0.00" description="" />
+ <keyValuePair key="bufr_available" value="16" description="" />
+ <keyValuePair key="bufr_fixed" value="0" description="" />
+ <keyValuePair key="bufr_used" value="0" description="" />
+ <keyValuePair key="bufr_util_percentage" value="0.00" description="" />
+ <keyValuePair key="mmcme2_adv_available" value="4" description="" />
+ <keyValuePair key="mmcme2_adv_fixed" value="0" description="" />
+ <keyValuePair key="mmcme2_adv_used" value="0" description="" />
+ <keyValuePair key="mmcme2_adv_util_percentage" value="0.00" description="" />
+ <keyValuePair key="plle2_adv_available" value="4" description="" />
+ <keyValuePair key="plle2_adv_fixed" value="0" description="" />
+ <keyValuePair key="plle2_adv_used" value="0" description="" />
+ <keyValuePair key="plle2_adv_util_percentage" value="0.00" description="" />
+ </section>
+ <section name="dsp" level="2" order="2" description="">
+ <keyValuePair key="dsps_available" value="220" description="" />
+ <keyValuePair key="dsps_fixed" value="0" description="" />
+ <keyValuePair key="dsps_used" value="0" description="" />
+ <keyValuePair key="dsps_util_percentage" value="0.00" description="" />
+ </section>
+ <section name="io_standard" level="2" order="3" description="">
+ <keyValuePair key="blvds_25" value="0" description="" />
+ <keyValuePair key="diff_hstl_i" value="0" description="" />
+ <keyValuePair key="diff_hstl_i_18" value="0" description="" />
+ <keyValuePair key="diff_hstl_ii" value="0" description="" />
+ <keyValuePair key="diff_hstl_ii_18" value="0" description="" />
+ <keyValuePair key="diff_hsul_12" value="0" description="" />
+ <keyValuePair key="diff_mobile_ddr" value="0" description="" />
+ <keyValuePair key="diff_sstl135" value="0" description="" />
+ <keyValuePair key="diff_sstl135_r" value="0" description="" />
+ <keyValuePair key="diff_sstl15" value="1" description="" />
+ <keyValuePair key="diff_sstl15_r" value="0" description="" />
+ <keyValuePair key="diff_sstl18_i" value="0" description="" />
+ <keyValuePair key="diff_sstl18_ii" value="0" description="" />
+ <keyValuePair key="hstl_i" value="0" description="" />
+ <keyValuePair key="hstl_i_18" value="0" description="" />
+ <keyValuePair key="hstl_ii" value="0" description="" />
+ <keyValuePair key="hstl_ii_18" value="0" description="" />
+ <keyValuePair key="hsul_12" value="0" description="" />
+ <keyValuePair key="lvcmos12" value="0" description="" />
+ <keyValuePair key="lvcmos15" value="0" description="" />
+ <keyValuePair key="lvcmos18" value="1" description="" />
+ <keyValuePair key="lvcmos25" value="0" description="" />
+ <keyValuePair key="lvcmos33" value="1" description="" />
+ <keyValuePair key="lvds_25" value="0" description="" />
+ <keyValuePair key="lvttl" value="0" description="" />
+ <keyValuePair key="mini_lvds_25" value="0" description="" />
+ <keyValuePair key="mobile_ddr" value="0" description="" />
+ <keyValuePair key="pci33_3" value="0" description="" />
+ <keyValuePair key="ppds_25" value="0" description="" />
+ <keyValuePair key="rsds_25" value="0" description="" />
+ <keyValuePair key="sstl135" value="0" description="" />
+ <keyValuePair key="sstl135_r" value="0" description="" />
+ <keyValuePair key="sstl15" value="1" description="" />
+ <keyValuePair key="sstl15_r" value="0" description="" />
+ <keyValuePair key="sstl18_i" value="0" description="" />
+ <keyValuePair key="sstl18_ii" value="0" description="" />
+ <keyValuePair key="tmds_33" value="0" description="" />
+ </section>
+ <section name="memory" level="2" order="4" description="">
+ <keyValuePair key="block_ram_tile_available" value="140" description="" />
+ <keyValuePair key="block_ram_tile_fixed" value="0" description="" />
+ <keyValuePair key="block_ram_tile_used" value="2" description="" />
+ <keyValuePair key="block_ram_tile_util_percentage" value="1.43" description="" />
+ <keyValuePair key="ramb18_available" value="280" description="" />
+ <keyValuePair key="ramb18_fixed" value="0" description="" />
+ <keyValuePair key="ramb18_used" value="0" description="" />
+ <keyValuePair key="ramb18_util_percentage" value="0.00" description="" />
+ <keyValuePair key="ramb36_fifo_available" value="140" description="" />
+ <keyValuePair key="ramb36_fifo_fixed" value="0" description="" />
+ <keyValuePair key="ramb36_fifo_used" value="2" description="" />
+ <keyValuePair key="ramb36_fifo_util_percentage" value="1.43" description="" />
+ <keyValuePair key="ramb36e1_only_used" value="2" description="" />
+ </section>
+ <section name="primitives" level="2" order="5" description="">
+ <keyValuePair key="bibuf_functional_category" value="IO" description="" />
+ <keyValuePair key="bibuf_used" value="130" description="" />
+ <keyValuePair key="bufg_functional_category" value="Clock" description="" />
+ <keyValuePair key="bufg_used" value="1" description="" />
+ <keyValuePair key="carry4_functional_category" value="CarryLogic" description="" />
+ <keyValuePair key="carry4_used" value="93" description="" />
+ <keyValuePair key="fdce_functional_category" value="Flop & Latch" description="" />
+ <keyValuePair key="fdce_used" value="69" description="" />
+ <keyValuePair key="fdpe_functional_category" value="Flop & Latch" description="" />
+ <keyValuePair key="fdpe_used" value="33" description="" />
+ <keyValuePair key="fdre_functional_category" value="Flop & Latch" description="" />
+ <keyValuePair key="fdre_used" value="3852" description="" />
+ <keyValuePair key="fdse_functional_category" value="Flop & Latch" description="" />
+ <keyValuePair key="fdse_used" value="121" description="" />
+ <keyValuePair key="lut1_functional_category" value="LUT" description="" />
+ <keyValuePair key="lut1_used" value="86" description="" />
+ <keyValuePair key="lut2_functional_category" value="LUT" description="" />
+ <keyValuePair key="lut2_used" value="466" description="" />
+ <keyValuePair key="lut3_functional_category" value="LUT" description="" />
+ <keyValuePair key="lut3_used" value="1004" description="" />
+ <keyValuePair key="lut4_functional_category" value="LUT" description="" />
+ <keyValuePair key="lut4_used" value="615" description="" />
+ <keyValuePair key="lut5_functional_category" value="LUT" description="" />
+ <keyValuePair key="lut5_used" value="584" description="" />
+ <keyValuePair key="lut6_functional_category" value="LUT" description="" />
+ <keyValuePair key="lut6_used" value="790" description="" />
+ <keyValuePair key="ps7_functional_category" value="Specialized Resource" description="" />
+ <keyValuePair key="ps7_used" value="1" description="" />
+ <keyValuePair key="ramb36e1_functional_category" value="Block Memory" description="" />
+ <keyValuePair key="ramb36e1_used" value="2" description="" />
+ <keyValuePair key="ramd32_functional_category" value="Distributed Memory" description="" />
+ <keyValuePair key="ramd32_used" value="26" description="" />
+ <keyValuePair key="rams32_functional_category" value="Distributed Memory" description="" />
+ <keyValuePair key="rams32_used" value="8" description="" />
+ <keyValuePair key="srl16e_functional_category" value="Distributed Memory" description="" />
+ <keyValuePair key="srl16e_used" value="196" description="" />
+ <keyValuePair key="srlc32e_functional_category" value="Distributed Memory" description="" />
+ <keyValuePair key="srlc32e_used" value="89" description="" />
+ </section>
+ <section name="slice_logic" level="2" order="6" description="">
+ <keyValuePair key="f7_muxes_available" value="26600" description="" />
+ <keyValuePair key="f7_muxes_fixed" value="0" description="" />
+ <keyValuePair key="f7_muxes_used" value="0" description="" />
+ <keyValuePair key="f7_muxes_util_percentage" value="0.00" description="" />
+ <keyValuePair key="f8_muxes_available" value="13300" description="" />
+ <keyValuePair key="f8_muxes_fixed" value="0" description="" />
+ <keyValuePair key="f8_muxes_used" value="0" description="" />
+ <keyValuePair key="f8_muxes_util_percentage" value="0.00" description="" />
+ <keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
+ <keyValuePair key="lut_as_distributed_ram_fixed" value="0" description="" />
+ <keyValuePair key="lut_as_distributed_ram_used" value="18" description="" />
+ <keyValuePair key="lut_as_distributed_ram_used" value="18" description="" />
+ <keyValuePair key="lut_as_logic_available" value="53200" description="" />
+ <keyValuePair key="lut_as_logic_available" value="53200" description="" />
+ <keyValuePair key="lut_as_logic_fixed" value="0" description="" />
+ <keyValuePair key="lut_as_logic_fixed" value="0" description="" />
+ <keyValuePair key="lut_as_logic_used" value="2762" description="" />
+ <keyValuePair key="lut_as_logic_used" value="2762" description="" />
+ <keyValuePair key="lut_as_logic_util_percentage" value="5.19" description="" />
+ <keyValuePair key="lut_as_logic_util_percentage" value="5.19" description="" />
+ <keyValuePair key="lut_as_memory_available" value="17400" description="" />
+ <keyValuePair key="lut_as_memory_available" value="17400" description="" />
+ <keyValuePair key="lut_as_memory_fixed" value="0" description="" />
+ <keyValuePair key="lut_as_memory_fixed" value="0" description="" />
+ <keyValuePair key="lut_as_memory_used" value="223" description="" />
+ <keyValuePair key="lut_as_memory_used" value="223" description="" />
+ <keyValuePair key="lut_as_memory_util_percentage" value="1.28" description="" />
+ <keyValuePair key="lut_as_memory_util_percentage" value="1.28" description="" />
+ <keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
+ <keyValuePair key="lut_as_shift_register_fixed" value="0" description="" />
+ <keyValuePair key="lut_as_shift_register_used" value="205" description="" />
+ <keyValuePair key="lut_as_shift_register_used" value="205" description="" />
+ <keyValuePair key="lut_in_front_of_the_register_is_unused_fixed" value="205" description="" />
+ <keyValuePair key="lut_in_front_of_the_register_is_unused_used" value="1372" description="" />
+ <keyValuePair key="lut_in_front_of_the_register_is_used_fixed" value="1372" description="" />
+ <keyValuePair key="lut_in_front_of_the_register_is_used_used" value="404" description="" />
+ <keyValuePair key="register_as_flip_flop_available" value="106400" description="" />
+ <keyValuePair key="register_as_flip_flop_fixed" value="0" description="" />
+ <keyValuePair key="register_as_flip_flop_used" value="4075" description="" />
+ <keyValuePair key="register_as_flip_flop_util_percentage" value="3.83" description="" />
+ <keyValuePair key="register_as_latch_available" value="106400" description="" />
+ <keyValuePair key="register_as_latch_fixed" value="0" description="" />
+ <keyValuePair key="register_as_latch_used" value="0" description="" />
+ <keyValuePair key="register_as_latch_util_percentage" value="0.00" description="" />
+ <keyValuePair key="register_driven_from_outside_the_slice_fixed" value="404" description="" />
+ <keyValuePair key="register_driven_from_outside_the_slice_used" value="1776" description="" />
+ <keyValuePair key="register_driven_from_within_the_slice_fixed" value="1776" description="" />
+ <keyValuePair key="register_driven_from_within_the_slice_used" value="2299" description="" />
+ <keyValuePair key="slice_available" value="13300" description="" />
+ <keyValuePair key="slice_fixed" value="0" description="" />
+ <keyValuePair key="slice_luts_available" value="53200" description="" />
+ <keyValuePair key="slice_luts_fixed" value="0" description="" />
+ <keyValuePair key="slice_luts_used" value="2985" description="" />
+ <keyValuePair key="slice_luts_util_percentage" value="5.61" description="" />
+ <keyValuePair key="slice_registers_available" value="106400" description="" />
+ <keyValuePair key="slice_registers_available" value="106400" description="" />
+ <keyValuePair key="slice_registers_fixed" value="0" description="" />
+ <keyValuePair key="slice_registers_fixed" value="0" description="" />
+ <keyValuePair key="slice_registers_used" value="4075" description="" />
+ <keyValuePair key="slice_registers_used" value="4075" description="" />
+ <keyValuePair key="slice_registers_util_percentage" value="3.83" description="" />
+ <keyValuePair key="slice_registers_util_percentage" value="3.83" description="" />
+ <keyValuePair key="slice_used" value="1342" description="" />
+ <keyValuePair key="slice_util_percentage" value="10.09" description="" />
+ <keyValuePair key="slicel_fixed" value="0" description="" />
+ <keyValuePair key="slicel_used" value="820" description="" />
+ <keyValuePair key="slicem_fixed" value="0" description="" />
+ <keyValuePair key="slicem_used" value="522" description="" />
+ <keyValuePair key="unique_control_sets_available" value="13300" description="" />
+ <keyValuePair key="unique_control_sets_fixed" value="13300" description="" />
+ <keyValuePair key="unique_control_sets_used" value="212" description="" />
+ <keyValuePair key="unique_control_sets_util_percentage" value="1.59" description="" />
+ <keyValuePair key="using_o5_and_o6_fixed" value="1.59" description="" />
+ <keyValuePair key="using_o5_and_o6_used" value="80" description="" />
+ <keyValuePair key="using_o5_output_only_fixed" value="80" description="" />
+ <keyValuePair key="using_o5_output_only_used" value="0" description="" />
+ <keyValuePair key="using_o6_output_only_fixed" value="0" description="" />
+ <keyValuePair key="using_o6_output_only_used" value="125" description="" />
+ </section>
+ <section name="specific_feature" level="2" order="7" description="">
+ <keyValuePair key="bscane2_available" value="4" description="" />
+ <keyValuePair key="bscane2_fixed" value="0" description="" />
+ <keyValuePair key="bscane2_used" value="0" description="" />
+ <keyValuePair key="bscane2_util_percentage" value="0.00" description="" />
+ <keyValuePair key="capturee2_available" value="1" description="" />
+ <keyValuePair key="capturee2_fixed" value="0" description="" />
+ <keyValuePair key="capturee2_used" value="0" description="" />
+ <keyValuePair key="capturee2_util_percentage" value="0.00" description="" />
+ <keyValuePair key="dna_port_available" value="1" description="" />
+ <keyValuePair key="dna_port_fixed" value="0" description="" />
+ <keyValuePair key="dna_port_used" value="0" description="" />
+ <keyValuePair key="dna_port_util_percentage" value="0.00" description="" />
+ <keyValuePair key="efuse_usr_available" value="1" description="" />
+ <keyValuePair key="efuse_usr_fixed" value="0" description="" />
+ <keyValuePair key="efuse_usr_used" value="0" description="" />
+ <keyValuePair key="efuse_usr_util_percentage" value="0.00" description="" />
+ <keyValuePair key="frame_ecce2_available" value="1" description="" />
+ <keyValuePair key="frame_ecce2_fixed" value="0" description="" />
+ <keyValuePair key="frame_ecce2_used" value="0" description="" />
+ <keyValuePair key="frame_ecce2_util_percentage" value="0.00" description="" />
+ <keyValuePair key="icape2_available" value="2" description="" />
+ <keyValuePair key="icape2_fixed" value="0" description="" />
+ <keyValuePair key="icape2_used" value="0" description="" />
+ <keyValuePair key="icape2_util_percentage" value="0.00" description="" />
+ <keyValuePair key="startupe2_available" value="1" description="" />
+ <keyValuePair key="startupe2_fixed" value="0" description="" />
+ <keyValuePair key="startupe2_used" value="0" description="" />
+ <keyValuePair key="startupe2_util_percentage" value="0.00" description="" />
+ <keyValuePair key="xadc_available" value="1" description="" />
+ <keyValuePair key="xadc_fixed" value="0" description="" />
+ <keyValuePair key="xadc_used" value="0" description="" />
+ <keyValuePair key="xadc_util_percentage" value="0.00" description="" />
+ </section>
+ </section>
+ <section name="synthesis" level="1" order="10" description="">
+ <section name="command_line_options" level="2" order="1" description="">
+ <keyValuePair key="-assert" value="default::[not_specified]" description="" />
+ <keyValuePair key="-bufg" value="default::12" description="" />
+ <keyValuePair key="-cascade_dsp" value="default::auto" description="" />
+ <keyValuePair key="-constrset" value="default::[not_specified]" description="" />
+ <keyValuePair key="-control_set_opt_threshold" value="default::auto" description="" />
+ <keyValuePair key="-debug_log" value="default::[not_specified]" description="" />
+ <keyValuePair key="-directive" value="default::default" description="" />
+ <keyValuePair key="-fanout_limit" value="default::10000" description="" />
+ <keyValuePair key="-flatten_hierarchy" value="default::rebuilt" description="" />
+ <keyValuePair key="-fsm_extraction" value="default::auto" description="" />
+ <keyValuePair key="-gated_clock_conversion" value="default::off" description="" />
+ <keyValuePair key="-generic" value="default::[not_specified]" description="" />
+ <keyValuePair key="-include_dirs" value="default::[not_specified]" description="" />
+ <keyValuePair key="-keep_equivalent_registers" value="default::[not_specified]" description="" />
+ <keyValuePair key="-lint" value="default::[not_specified]" description="" />
+ <keyValuePair key="-max_bram" value="default::-1" description="" />
+ <keyValuePair key="-max_bram_cascade_height" value="default::-1" description="" />
+ <keyValuePair key="-max_dsp" value="default::-1" description="" />
+ <keyValuePair key="-max_uram" value="default::-1" description="" />
+ <keyValuePair key="-max_uram_cascade_height" value="default::-1" description="" />
+ <keyValuePair key="-mode" value="default::default" description="" />
+ <keyValuePair key="-name" value="default::[not_specified]" description="" />
+ <keyValuePair key="-no_lc" value="default::[not_specified]" description="" />
+ <keyValuePair key="-no_srlextract" value="default::[not_specified]" description="" />
+ <keyValuePair key="-no_timing_driven" value="default::[not_specified]" description="" />
+ <keyValuePair key="-os" value="default::[not_specified]" description="" />
+ <keyValuePair key="-part" value="xc7z020clg400-1" description="" />
+ <keyValuePair key="-resource_sharing" value="default::auto" description="" />
+ <keyValuePair key="-retiming" value="default::[not_specified]" description="" />
+ <keyValuePair key="-rtl" value="default::[not_specified]" description="" />
+ <keyValuePair key="-rtl_skip_constraints" value="default::[not_specified]" description="" />
+ <keyValuePair key="-rtl_skip_ip" value="default::[not_specified]" description="" />
+ <keyValuePair key="-seu_protect" value="default::none" description="" />
+ <keyValuePair key="-sfcu" value="default::[not_specified]" description="" />
+ <keyValuePair key="-shreg_min_size" value="default::3" description="" />
+ <keyValuePair key="-top" value="overlay" description="" />
+ <keyValuePair key="-verilog_define" value="default::[not_specified]" description="" />
+ </section>
+ <section name="usage" level="2" order="2" description="">
+ <keyValuePair key="elapsed" value="00:00:34s" description="" />
+ <keyValuePair key="hls_ip" value="0" description="" />
+ <keyValuePair key="memory_gain" value="64.031MB" description="" />
+ <keyValuePair key="memory_peak" value="2352.094MB" description="" />
+ </section>
+ </section>
+ <section name="unisim_transformation" level="1" order="11" description="">
+ <section name="post_unisim_transformation" level="2" order="1" description="">
+ <keyValuePair key="bibuf" value="130" description="" />
+ <keyValuePair key="bufg" value="1" description="" />
+ <keyValuePair key="carry4" value="101" description="" />
+ <keyValuePair key="fdce" value="69" description="" />
+ <keyValuePair key="fdpe" value="33" description="" />
+ <keyValuePair key="fdre" value="4265" description="" />
+ <keyValuePair key="fdse" value="122" description="" />
+ <keyValuePair key="gnd" value="175" description="" />
+ <keyValuePair key="lut1" value="162" description="" />
+ <keyValuePair key="lut2" value="491" description="" />
+ <keyValuePair key="lut3" value="1059" description="" />
+ <keyValuePair key="lut4" value="527" description="" />
+ <keyValuePair key="lut5" value="649" description="" />
+ <keyValuePair key="lut6" value="1053" description="" />
+ <keyValuePair key="ps7" value="1" description="" />
+ <keyValuePair key="ramb36e1" value="2" description="" />
+ <keyValuePair key="ramd32" value="26" description="" />
+ <keyValuePair key="rams32" value="8" description="" />
+ <keyValuePair key="srl16e" value="193" description="" />
+ <keyValuePair key="srlc32e" value="106" description="" />
+ <keyValuePair key="vcc" value="178" description="" />
+ </section>
+ <section name="pre_unisim_transformation" level="2" order="2" description="">
+ <keyValuePair key="bibuf" value="130" description="" />
+ <keyValuePair key="bufg" value="1" description="" />
+ <keyValuePair key="carry4" value="101" description="" />
+ <keyValuePair key="fdce" value="69" description="" />
+ <keyValuePair key="fdpe" value="33" description="" />
+ <keyValuePair key="fdre" value="4265" description="" />
+ <keyValuePair key="fdse" value="122" description="" />
+ <keyValuePair key="gnd" value="175" description="" />
+ <keyValuePair key="lut1" value="162" description="" />
+ <keyValuePair key="lut2" value="491" description="" />
+ <keyValuePair key="lut3" value="1059" description="" />
+ <keyValuePair key="lut4" value="527" description="" />
+ <keyValuePair key="lut5" value="649" description="" />
+ <keyValuePair key="lut6" value="1053" description="" />
+ <keyValuePair key="ps7" value="1" description="" />
+ <keyValuePair key="ram32m" value="4" description="" />
+ <keyValuePair key="ram32x1d" value="1" description="" />
+ <keyValuePair key="ramb36e1" value="2" description="" />
+ <keyValuePair key="srl16e" value="193" description="" />
+ <keyValuePair key="srlc32e" value="106" description="" />
+ <keyValuePair key="vcc" value="178" description="" />
+ </section>
+ </section>
+ <section name="vivado_usage" level="1" order="12" description="">
+ <section name="other_data" level="2" order="1" description="">
+ <keyValuePair key="guimode" value="1" description="" />
+ <keyValuePair key="tclmode" value="3" description="" />
+ </section>
+ <section name="project_data" level="2" order="2" description="">
+ <keyValuePair key="constraintsetcount" value="0" description="" />
+ <keyValuePair key="core_container" value="false" description="" />
+ <keyValuePair key="currentimplrun" value="impl_1" description="" />
+ <keyValuePair key="currentsynthesisrun" value="synth_1" description="" />
+ <keyValuePair key="default_library" value="xil_defaultlib" description="" />
+ <keyValuePair key="designmode" value="RTL" description="" />
+ <keyValuePair key="export_simulation_activehdl" value="0" description="" />
+ <keyValuePair key="export_simulation_ies" value="0" description="" />
+ <keyValuePair key="export_simulation_modelsim" value="0" description="" />
+ <keyValuePair key="export_simulation_questa" value="0" description="" />
+ <keyValuePair key="export_simulation_riviera" value="0" description="" />
+ <keyValuePair key="export_simulation_vcs" value="0" description="" />
+ <keyValuePair key="export_simulation_xsim" value="0" description="" />
+ <keyValuePair key="implstrategy" value="Vivado Implementation Defaults" description="" />
+ <keyValuePair key="launch_simulation_activehdl" value="0" description="" />
+ <keyValuePair key="launch_simulation_ies" value="0" description="" />
+ <keyValuePair key="launch_simulation_modelsim" value="0" description="" />
+ <keyValuePair key="launch_simulation_questa" value="0" description="" />
+ <keyValuePair key="launch_simulation_riviera" value="0" description="" />
+ <keyValuePair key="launch_simulation_vcs" value="0" description="" />
+ <keyValuePair key="launch_simulation_xsim" value="0" description="" />
+ <keyValuePair key="simulator_language" value="Mixed" description="" />
+ <keyValuePair key="srcsetcount" value="1" description="" />
+ <keyValuePair key="synthesisstrategy" value="Vivado Synthesis Defaults" description="" />
+ <keyValuePair key="target_language" value="Verilog" description="" />
+ <keyValuePair key="target_simulator" value="XSim" description="" />
+ <keyValuePair key="totalimplruns" value="11" description="" />
+ <keyValuePair key="totalsynthesisruns" value="11" description="" />
+ </section>
+ </section>
+</section>
+</webTalkData>
diff --git a/rtl-proj/rtl.runs/impl_1/vivado.jou b/rtl-proj/rtl.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..d6972e1e4f1d1d02adcff15335339c4c7a986ead
--- /dev/null
+++ b/rtl-proj/rtl.runs/impl_1/vivado.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2020.2 (64-bit)
+# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
+# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+# Start of session at: Fri Jun 4 02:05:15 2021
+# Process ID: 1655663
+# Current directory: /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1
+# Command line: vivado -log overlay.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source overlay.tcl -notrace
+# Log file: /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/overlay.vdi
+# Journal file: /home/mh02127/pixel_manipulation/embedded-security-project/rtl-proj/rtl.runs/impl_1/vivado.jou
+#-----------------------------------------------------------
+source overlay.tcl -notrace
diff --git a/rtl-proj/rtl.runs/impl_1/vivado.pb b/rtl-proj/rtl.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..ab7966c1fda0483b0997dd6f5dffecf6b38d2bfb
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/vivado.pb differ
diff --git a/rtl-proj/rtl.runs/impl_1/write_bitstream.pb b/rtl-proj/rtl.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000000000000000000000000000000000000..2928a28013838109d54c625cf55684d1fd028ac7
Binary files /dev/null and b/rtl-proj/rtl.runs/impl_1/write_bitstream.pb differ