diff --git a/overlay.bit b/overlay.bit
index a3a8492a615907ad8fa96d0a9c518c7a5790529c..217200bb05fe4c3d6cb6f4da497864dc8bb1bc07 100644
Binary files a/overlay.bit and b/overlay.bit differ
diff --git a/overlay.hwh b/overlay.hwh
index dbc5a6b70e3c097d77e560e866776a6d37727bf6..0786be0d0d543483432aebd87b634135138e3429 100644
--- a/overlay.hwh
+++ b/overlay.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Jun 3 03:43:53 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Jun 3 04:54:56 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
@@ -3471,6 +3471,95 @@
<PORT DIR="O" NAME="S02_AXI_rlast" SIGIS="undef"/>
<PORT DIR="O" NAME="S02_AXI_rvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S02_AXI_rready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
<PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_1_m_axi_s2mm_awaddr">
<CONNECTIONS>
@@ -3759,95 +3848,6 @@
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="O" LEFT="1" NAME="M00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="axi_interconnect_0_M00_AXI_wid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WID"/>
@@ -4065,7 +4065,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106030336" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106030449" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
@@ -4090,6 +4090,26 @@
</FIELD>
</FIELDS>
</REGISTER>
+ <REGISTER NAME="len">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of len"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+ <FIELDS>
+ <FIELD NAME="len">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of len"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
</REGISTERS>
</ADDRESSBLOCK>
</ADDRESSBLOCKS>
@@ -6418,6 +6438,109 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="O" LEFT="31" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M02_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M02_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M02_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M02_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M02_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M02_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M02_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M02_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M02_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M02_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M02_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M02_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M02_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M02_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M02_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
@@ -6616,109 +6739,6 @@
<CONNECTION INSTANCE="axi_dma_1" PORT="s_axi_lite_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M02_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M02_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M02_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M02_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M02_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M02_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M02_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M02_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M02_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M02_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M02_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M02_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M02_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M02_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M02_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>