diff --git a/overlay.bit b/overlay.bit
index a5bb949e0426575682d174a7d0a92e640fbd220d..40e4929c0b5e628916cae7facbe5bfd6ead1f80f 100644
Binary files a/overlay.bit and b/overlay.bit differ
diff --git a/overlay.hwh b/overlay.hwh
index d5f003dcd1e64758ef3c46ef938d94d0e2e1fb03..9b21a99145fcda87705aa26cf8482522b55255a0 100644
--- a/overlay.hwh
+++ b/overlay.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sun Jun 13 01:55:53 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Jun 16 13:22:22 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
@@ -1912,383 +1912,383 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
+ <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
+ <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
+ <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
+ <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
+ <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
+ <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
+ <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
+ <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
+ <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
+ <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
+ <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
+ <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
+ <PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
+ <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
+ <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
+ <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
+ <PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
+ <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
+ <PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
+ <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
+ <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
+ <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
+ <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
+ <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
+ <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
+ <PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
+ <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
+ <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WID"/>
@@ -2424,7 +2424,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106130151" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106161309" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
@@ -2489,16 +2489,16 @@
</FIELD>
</FIELDS>
</REGISTER>
- <REGISTER NAME="character_r">
- <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of character_r"/>
+ <REGISTER NAME="ascii">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ascii"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="40"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
- <FIELD NAME="character_r">
- <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of character_r"/>
+ <FIELD NAME="ascii">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of ascii"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
@@ -4719,269 +4719,104 @@
<PARAMETER NAME="M21_SECURE" VALUE="0"/>
<PARAMETER NAME="M22_SECURE" VALUE="0"/>
<PARAMETER NAME="M23_SECURE" VALUE="0"/>
- <PARAMETER NAME="M24_SECURE" VALUE="0"/>
- <PARAMETER NAME="M25_SECURE" VALUE="0"/>
- <PARAMETER NAME="M26_SECURE" VALUE="0"/>
- <PARAMETER NAME="M27_SECURE" VALUE="0"/>
- <PARAMETER NAME="M28_SECURE" VALUE="0"/>
- <PARAMETER NAME="M29_SECURE" VALUE="0"/>
- <PARAMETER NAME="M30_SECURE" VALUE="0"/>
- <PARAMETER NAME="M31_SECURE" VALUE="0"/>
- <PARAMETER NAME="M32_SECURE" VALUE="0"/>
- <PARAMETER NAME="M33_SECURE" VALUE="0"/>
- <PARAMETER NAME="M34_SECURE" VALUE="0"/>
- <PARAMETER NAME="M35_SECURE" VALUE="0"/>
- <PARAMETER NAME="M36_SECURE" VALUE="0"/>
- <PARAMETER NAME="M37_SECURE" VALUE="0"/>
- <PARAMETER NAME="M38_SECURE" VALUE="0"/>
- <PARAMETER NAME="M39_SECURE" VALUE="0"/>
- <PARAMETER NAME="M40_SECURE" VALUE="0"/>
- <PARAMETER NAME="M41_SECURE" VALUE="0"/>
- <PARAMETER NAME="M42_SECURE" VALUE="0"/>
- <PARAMETER NAME="M43_SECURE" VALUE="0"/>
- <PARAMETER NAME="M44_SECURE" VALUE="0"/>
- <PARAMETER NAME="M45_SECURE" VALUE="0"/>
- <PARAMETER NAME="M46_SECURE" VALUE="0"/>
- <PARAMETER NAME="M47_SECURE" VALUE="0"/>
- <PARAMETER NAME="M48_SECURE" VALUE="0"/>
- <PARAMETER NAME="M49_SECURE" VALUE="0"/>
- <PARAMETER NAME="M50_SECURE" VALUE="0"/>
- <PARAMETER NAME="M51_SECURE" VALUE="0"/>
- <PARAMETER NAME="M52_SECURE" VALUE="0"/>
- <PARAMETER NAME="M53_SECURE" VALUE="0"/>
- <PARAMETER NAME="M54_SECURE" VALUE="0"/>
- <PARAMETER NAME="M55_SECURE" VALUE="0"/>
- <PARAMETER NAME="M56_SECURE" VALUE="0"/>
- <PARAMETER NAME="M57_SECURE" VALUE="0"/>
- <PARAMETER NAME="M58_SECURE" VALUE="0"/>
- <PARAMETER NAME="M59_SECURE" VALUE="0"/>
- <PARAMETER NAME="M60_SECURE" VALUE="0"/>
- <PARAMETER NAME="M61_SECURE" VALUE="0"/>
- <PARAMETER NAME="M62_SECURE" VALUE="0"/>
- <PARAMETER NAME="M63_SECURE" VALUE="0"/>
- <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
- <PARAMETER NAME="Component_Name" VALUE="overlay_ps_axi_periph_0"/>
- <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
- </PARAMETERS>
- <PORTS>
- <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
- <CONNECTIONS>
- <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLEN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWSIZE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWBURST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLOCK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWCACHE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWQOS"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WSTRB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WLAST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLEN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARSIZE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARBURST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLOCK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARCACHE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
+ <PARAMETER NAME="M24_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M25_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M26_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M27_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M28_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M29_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M30_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M31_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M32_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M33_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M34_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M35_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M36_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M37_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M38_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M39_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M40_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M41_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M42_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M43_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M44_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M45_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+ <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_ps_axi_periph_0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARQOS"/>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
+ <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARVALID"/>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
+ <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
+ <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RDATA"/>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RRESP">
+ <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RRESP"/>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
+ <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RLAST"/>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RVALID">
+ <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
+ <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
@@ -5186,6 +5021,171 @@
<CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WSTRB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARID"/>