diff --git a/main.cpp b/main.cpp
index 8b117e7e2b2407d2f7aaa3fb602b5286a1c33566..adadeaf71526fc72a822d0a798169da591752ebc 100644
--- a/main.cpp
+++ b/main.cpp
@@ -31,7 +31,7 @@ int main() {
for (int x = 0; x < 2; x++) {
for (int z = 0;z < 2; z++){
pkt_t tmp = streamOut.read();
- printf("%d",tmp.data);
+
}
}
}
diff --git a/overlay.bit b/overlay.bit
index 8bf511f05745c61585260d7ca7e7b400f4eb5a5a..17afe4b1b331089289e1bb62dae8f720cd4eb90c 100644
Binary files a/overlay.bit and b/overlay.bit differ
diff --git a/overlay.hwh b/overlay.hwh
index 5139bde9fda025f57bed96507301d838cd8e54f0..1301e8b5a976dcdca27bcc982704fd014589e212 100644
--- a/overlay.hwh
+++ b/overlay.hwh
@@ -1,9 +1,39 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Wed Jun 23 13:06:22 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Jun 25 00:45:28 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
+ <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="MIO"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="ps_DDR_CAS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="DDR_CAS_n"/>
@@ -79,36 +109,6 @@
<CONNECTION INSTANCE="ps" PORT="DDR_DQS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="MIO"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
- </CONNECTIONS>
- </PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
@@ -1912,95 +1912,6 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
<PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS>
@@ -2102,6 +2013,95 @@
<PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
@@ -2424,58 +2424,28 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106231301" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106250038" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
<REGISTERS>
- <REGISTER NAME="key">
- <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of key"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <REGISTER NAME="selector">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of selector"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
- <FIELD NAME="key">
- <PROPERTY NAME="DESCRIPTION" VALUE="Bit 7 to 0 of key"/>
+ <FIELD NAME="selector">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of selector"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
<PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
<PROPERTY NAME="READ_ACTION" VALUE=""/>
<PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
- <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
- </FIELD>
- <FIELD NAME="RESERVED">
- <PROPERTY NAME="DESCRIPTION" VALUE="Reserved. 0s on read."/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
- <PROPERTY NAME="ACCESS" VALUE="read-only"/>
- <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
- <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
- <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
- <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
- <PROPERTY NAME="BIT_WIDTH" VALUE="24"/>
- </FIELD>
- </FIELDS>
- </REGISTER>
- <REGISTER NAME="selector">
- <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of selector"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
- <PROPERTY NAME="SIZE" VALUE="32"/>
- <PROPERTY NAME="ACCESS" VALUE="write-only"/>
- <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
- <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
- <FIELDS>
- <FIELD NAME="selector">
- <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of selector"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
- <PROPERTY NAME="ACCESS" VALUE="write-only"/>
- <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
- <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
- <PROPERTY NAME="READ_ACTION" VALUE=""/>
- <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
- <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
</FIELD>
</FIELDS>
</REGISTER>
@@ -2609,6 +2579,14 @@
</FIELD>
</FIELDS>
</REGISTER>
+ <REGISTER NAME="Memory_key">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Memory key"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="SIZE" VALUE="8"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+ </REGISTER>
</REGISTERS>
</ADDRESSBLOCK>
</ADDRESSBLOCKS>
@@ -4919,107 +4897,169 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLEN"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWSIZE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWBURST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLOCK"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWCACHE"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWPROT"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWQOS"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WSTRB"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WLAST"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
@@ -5121,169 +5161,107 @@
<CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLEN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWSIZE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWBURST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLOCK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWCACHE"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWPROT"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWQOS"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WSTRB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WLAST"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BVALID"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
+ <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BREADY"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARADDR">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARADDR"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLEN"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
+ <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARSIZE"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
+ <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARBURST"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLOCK"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARCACHE"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARPROT"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARQOS"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARVALID"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
+ <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARREADY"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RDATA"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RRESP">
+ <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RRESP"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RLAST"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RVALID">
+ <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RVALID"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">