diff --git a/overlay.bit b/overlay.bit
index 37bdb3f02e6b7ff3a4d2d030fb75ad36f7cfbae6..91be65a850677dc91762e8846170cfb578926dec 100644
Binary files a/overlay.bit and b/overlay.bit differ
diff --git a/overlay.hwh b/overlay.hwh
index 5fbf4ae809048d332b730e63dc2662fc6dc297e5..1a0852a153c0a217f2e31462eff2850914d61535 100644
--- a/overlay.hwh
+++ b/overlay.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Jun 25 10:48:09 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Jun 25 12:24:39 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
@@ -1912,95 +1912,6 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
<PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS>
@@ -2102,6 +2013,95 @@
<PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
@@ -2424,14 +2424,34 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106251043" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106251217" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
<REGISTERS>
+ <REGISTER NAME="xs">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of xs"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
+ <FIELDS>
+ <FIELD NAME="xs">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of xs"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="write-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
<REGISTER NAME="selector">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of selector"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="32"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2451,7 +2471,7 @@
</REGISTER>
<REGISTER NAME="position1">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of position1"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="40"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="32"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2471,7 +2491,7 @@
</REGISTER>
<REGISTER NAME="position2">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of position2"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="48"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="40"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2491,7 +2511,7 @@
</REGISTER>
<REGISTER NAME="stream_count">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of stream_count"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="56"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="48"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2511,7 +2531,7 @@
</REGISTER>
<REGISTER NAME="ascii_i">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ascii_i"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="64"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="56"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2531,7 +2551,7 @@
</REGISTER>
<REGISTER NAME="ascii_o">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ascii_o"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="72"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="64"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2551,7 +2571,7 @@
</REGISTER>
<REGISTER NAME="ascii_o_ctrl">
<PROPERTY NAME="DESCRIPTION" VALUE="Control signal of ascii_o"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="76"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="68"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2581,7 +2601,7 @@
</REGISTER>
<REGISTER NAME="keyout">
<PROPERTY NAME="DESCRIPTION" VALUE="Data signal of keyout"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="80"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="72"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2601,7 +2621,7 @@
</REGISTER>
<REGISTER NAME="keyout_ctrl">
<PROPERTY NAME="DESCRIPTION" VALUE="Control signal of keyout"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="84"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="76"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
@@ -2629,14 +2649,6 @@
</FIELD>
</FIELDS>
</REGISTER>
- <REGISTER NAME="Memory_key">
- <PROPERTY NAME="DESCRIPTION" VALUE="Memory key"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
- <PROPERTY NAME="SIZE" VALUE="16"/>
- <PROPERTY NAME="ACCESS" VALUE="read-write"/>
- <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
- <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
- </REGISTER>
</REGISTERS>
</ADDRESSBLOCK>
</ADDRESSBLOCKS>
@@ -5050,105 +5062,6 @@
<CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
@@ -5314,6 +5227,105 @@
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARID"/>