diff --git a/overlay.bit b/overlay.bit
index 91be65a850677dc91762e8846170cfb578926dec..5fb2433e1e43779ab1cd82267ddb24fdf09320f7 100644
Binary files a/overlay.bit and b/overlay.bit differ
diff --git a/overlay.hwh b/overlay.hwh
index 1a0852a153c0a217f2e31462eff2850914d61535..f223569105e54e621dd645cf7887d5a45f05fd55 100644
--- a/overlay.hwh
+++ b/overlay.hwh
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Jun 25 12:24:39 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sat Jun 26 17:23:53 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
@@ -2424,21 +2424,21 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106251217" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106261717" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
<REGISTERS>
- <REGISTER NAME="xs">
- <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of xs"/>
+ <REGISTER NAME="in_decimal">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of in_decimal"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
- <FIELD NAME="xs">
- <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of xs"/>
+ <FIELD NAME="in_decimal">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of in_decimal"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="write-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
@@ -2529,86 +2529,16 @@
</FIELD>
</FIELDS>
</REGISTER>
- <REGISTER NAME="ascii_i">
- <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ascii_i"/>
+ <REGISTER NAME="ascii">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ascii"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="56"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
- <PROPERTY NAME="ACCESS" VALUE="write-only"/>
- <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
- <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
- <FIELDS>
- <FIELD NAME="ascii_i">
- <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of ascii_i"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
- <PROPERTY NAME="ACCESS" VALUE="write-only"/>
- <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
- <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
- <PROPERTY NAME="READ_ACTION" VALUE=""/>
- <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
- <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
- </FIELD>
- </FIELDS>
- </REGISTER>
- <REGISTER NAME="ascii_o">
- <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of ascii_o"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="64"/>
- <PROPERTY NAME="SIZE" VALUE="32"/>
- <PROPERTY NAME="ACCESS" VALUE="read-only"/>
- <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
- <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
- <FIELDS>
- <FIELD NAME="ascii_o">
- <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of ascii_o"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
- <PROPERTY NAME="ACCESS" VALUE="read-only"/>
- <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
- <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
- <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
- <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
- <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
- </FIELD>
- </FIELDS>
- </REGISTER>
- <REGISTER NAME="ascii_o_ctrl">
- <PROPERTY NAME="DESCRIPTION" VALUE="Control signal of ascii_o"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="68"/>
- <PROPERTY NAME="SIZE" VALUE="32"/>
- <PROPERTY NAME="ACCESS" VALUE="read-only"/>
- <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
- <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
- <FIELDS>
- <FIELD NAME="ascii_o_ap_vld">
- <PROPERTY NAME="DESCRIPTION" VALUE="Control signal ascii_o_ap_vld"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
- <PROPERTY NAME="ACCESS" VALUE="read-only"/>
- <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
- <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
- <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
- <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
- <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
- </FIELD>
- <FIELD NAME="RESERVED">
- <PROPERTY NAME="DESCRIPTION" VALUE="Reserved. 0s on read."/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
- <PROPERTY NAME="ACCESS" VALUE="read-only"/>
- <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
- <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
- <PROPERTY NAME="READ_ACTION" VALUE="modify"/>
- <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
- <PROPERTY NAME="BIT_WIDTH" VALUE="31"/>
- </FIELD>
- </FIELDS>
- </REGISTER>
- <REGISTER NAME="keyout">
- <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of keyout"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="72"/>
- <PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
- <FIELD NAME="keyout">
- <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of keyout"/>
+ <FIELD NAME="ascii">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Bit 31 to 0 of ascii"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
@@ -2619,16 +2549,16 @@
</FIELD>
</FIELDS>
</REGISTER>
- <REGISTER NAME="keyout_ctrl">
- <PROPERTY NAME="DESCRIPTION" VALUE="Control signal of keyout"/>
- <PROPERTY NAME="ADDRESS_OFFSET" VALUE="76"/>
+ <REGISTER NAME="ascii_ctrl">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Control signal of ascii"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="60"/>
<PROPERTY NAME="SIZE" VALUE="32"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="IS_ENABLED" VALUE="true"/>
<PROPERTY NAME="RESET_VALUE" VALUE="0"/>
<FIELDS>
- <FIELD NAME="keyout_ap_vld">
- <PROPERTY NAME="DESCRIPTION" VALUE="Control signal keyout_ap_vld"/>
+ <FIELD NAME="ascii_ap_vld">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Control signal ascii_ap_vld"/>
<PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
<PROPERTY NAME="ACCESS" VALUE="read-only"/>
<PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
@@ -2653,7 +2583,7 @@
</ADDRESSBLOCK>
</ADDRESSBLOCKS>
<PARAMETERS>
- <PARAMETER NAME="C_S_AXI_CONTROL_ADDR_WIDTH" VALUE="7"/>
+ <PARAMETER NAME="C_S_AXI_CONTROL_ADDR_WIDTH" VALUE="6"/>
<PARAMETER NAME="C_S_AXI_CONTROL_DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="Component_Name" VALUE="overlay_pixel_0"/>
<PARAMETER NAME="clk_period" VALUE="10"/>
@@ -2666,7 +2596,7 @@
<PARAMETER NAME="C_S_AXI_CONTROL_HIGHADDR" VALUE="0x4000FFFF"/>
</PARAMETERS>
<PORTS>
- <PORT DIR="I" LEFT="6" NAME="s_axi_control_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
+ <PORT DIR="I" LEFT="5" NAME="s_axi_control_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_awaddr"/>
</CONNECTIONS>
@@ -2716,7 +2646,7 @@
<CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="6" NAME="s_axi_control_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
+ <PORT DIR="I" LEFT="5" NAME="s_axi_control_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="ps_axi_periph" PORT="M01_AXI_araddr"/>
</CONNECTIONS>
@@ -2816,7 +2746,7 @@
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="ps_axi_periph_M01_AXI" DATAWIDTH="32" NAME="s_axi_control" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
- <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
@@ -4959,109 +4889,6 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
@@ -5326,6 +5153,109 @@
<CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARID"/>