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Commit 667fc32b authored by Vipin Thomas's avatar Vipin Thomas
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new cjahes

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?> <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sat Jun 12 15:03:47 2021" VIVADOVERSION="2020.2"> <EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sat Jun 12 16:59:38 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/> <SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
...@@ -1912,381 +1912,381 @@ ...@@ -1912,381 +1912,381 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/> <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/> <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
<PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen"> <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize"> <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst"> <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/> <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
<PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot"> <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/> <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
<PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready"> <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata"> <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb"> <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast"> <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid"> <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready"> <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/> <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
<PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid"> <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready"> <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/> <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
<PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen"> <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize"> <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst"> <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/> <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
<PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot"> <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/> <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
<PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready"> <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/> <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
<PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp"> <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast"> <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid"> <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready"> <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid"> <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr"> <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen"> <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize"> <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst"> <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock"> <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache"> <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot"> <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/> <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/> <PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos"> <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid"> <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready"> <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata"> <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb"> <PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/>
<PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast"> <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid"> <PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready"> <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid"> <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp"> <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid"> <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready"> <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid"> <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr"> <PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/>
<PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen"> <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize"> <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst"> <PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
<PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock"> <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache"> <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot"> <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/> <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
<PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos"> <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid"> <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready"> <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
<PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid"> <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata"> <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
<PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp"> <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast"> <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid"> <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready"> <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
<CONNECTIONS> <CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/> <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
</CONNECTIONS> </CONNECTIONS>
</PORT> </PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wid"> <PORT DIR="O" LEFT="0" NAME="M00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wid">
...@@ -2424,7 +2424,7 @@ ...@@ -2424,7 +2424,7 @@
</BUSINTERFACE> </BUSINTERFACE>
</BUSINTERFACES> </BUSINTERFACES>
</MODULE> </MODULE>
<MODULE COREREVISION="2106121441" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0"> <MODULE COREREVISION="2106121650" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/> <DOCUMENTS/>
<ADDRESSBLOCKS> <ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register"> <ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
......
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