From 1c55c7bfd3894e51211e760de8df3ba145e7c462 Mon Sep 17 00:00:00 2001
From: Majd Hafiri <mh02127@joan.th-deg.de>
Date: Mon, 31 May 2021 23:13:45 +0200
Subject: [PATCH] added overlay and handoff
---
.../bd/overlay/hw_handoff/overlay.hwh | 4973 +++++++++++++++++
rtl-proj/rtl.runs/impl_1/overlay.bit | Bin 0 -> 4045667 bytes
2 files changed, 4973 insertions(+)
create mode 100644 rtl-proj/rtl.gen/sources_1/bd/overlay/hw_handoff/overlay.hwh
create mode 100644 rtl-proj/rtl.runs/impl_1/overlay.bit
diff --git a/rtl-proj/rtl.gen/sources_1/bd/overlay/hw_handoff/overlay.hwh b/rtl-proj/rtl.gen/sources_1/bd/overlay/hw_handoff/overlay.hwh
new file mode 100644
index 0000000..9d8eff1
--- /dev/null
+++ b/rtl-proj/rtl.gen/sources_1/bd/overlay/hw_handoff/overlay.hwh
@@ -0,0 +1,4973 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Mon May 31 22:42:48 2021" VIVADOVERSION="2020.2">
+
+ <SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
+
+ <EXTERNALPORTS>
+ <PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="ps_DDR_CAS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_CAS_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_cke" SIGIS="undef" SIGNAME="ps_DDR_CKE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_CKE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_n" SIGIS="clk" SIGNAME="ps_DDR_Clk_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_Clk_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="100000000" DIR="IO" NAME="DDR_ck_p" SIGIS="clk" SIGNAME="ps_DDR_Clk">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_Clk"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_cs_n" SIGIS="undef" SIGNAME="ps_DDR_CS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_CS_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_reset_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="ps_DDR_DRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_DRSTB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_odt" SIGIS="undef" SIGNAME="ps_DDR_ODT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_ODT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_ras_n" SIGIS="undef" SIGNAME="ps_DDR_RAS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_RAS_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_we_n" SIGIS="undef" SIGNAME="ps_DDR_WEB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_WEB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="2" NAME="DDR_ba" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_BankAddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_BankAddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="14" NAME="DDR_addr" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_Addr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_Addr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_dm" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DM">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_DM"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="31" NAME="DDR_dq" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQ">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_DQ"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_n" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_DQS_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_dqs_p" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_DQS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="MIO"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
+ </CONNECTIONS>
+ </PORT>
+ </EXTERNALPORTS>
+
+ <EXTERNALINTERFACES>
+ <BUSINTERFACE BUSNAME="ps_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR">
+ <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+ <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
+ <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
+ <PARAMETER NAME="MEMORY_PART"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
+ <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
+ <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
+ <PARAMETER NAME="SLOT" VALUE="Single"/>
+ <PARAMETER NAME="CUSTOM_PARTS"/>
+ <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
+ <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
+ <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
+ <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
+ <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_cas_n"/>
+ <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_cke"/>
+ <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_ck_n"/>
+ <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_ck_p"/>
+ <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_cs_n"/>
+ <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_reset_n"/>
+ <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_odt"/>
+ <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_ras_n"/>
+ <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_we_n"/>
+ <PORTMAP LOGICAL="BA" PHYSICAL="DDR_ba"/>
+ <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_addr"/>
+ <PORTMAP LOGICAL="DM" PHYSICAL="DDR_dm"/>
+ <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_dq"/>
+ <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_dqs_n"/>
+ <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_dqs_p"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="ps_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR">
+ <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="MIO" PHYSICAL="FIXED_IO_mio"/>
+ <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="FIXED_IO_ddr_vrn"/>
+ <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="FIXED_IO_ddr_vrp"/>
+ <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="FIXED_IO_ps_srstb"/>
+ <PORTMAP LOGICAL="PS_CLK" PHYSICAL="FIXED_IO_ps_clk"/>
+ <PORTMAP LOGICAL="PS_PORB" PHYSICAL="FIXED_IO_ps_porb"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </EXTERNALINTERFACES>
+
+ <MODULES>
+ <MODULE COREREVISION="23" FULLNAME="/axi_dma_0" HWVERSION="7.1" INSTANCE="axi_dma_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
+ </DOCUMENTS>
+ <ADDRESSBLOCKS>
+ <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
+ <REGISTERS>
+ <REGISTER NAME="MM2S_DMACR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Control Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
+ <FIELDS>
+ <FIELD NAME="RS">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.
 0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. 
 AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
 For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.
 The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
 1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Reset">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Normal operation. 1 - Reset in progress.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Keyhole">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.
This bit is non functional when the multichannel feature is enabled or in Direct Register mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Cyclic_BD_Enable">
+ <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.
This bit is non functional when DMA operates in multichannel mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="IOC_IrqEn">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Dly_IrqEn">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Err_IrqEn">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable.
 0 - Error Interrupt disabled
 1 - Error Interrupt enabled
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="IRQThreshold">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine. Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect. Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ <FIELD NAME="IRQDelay">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
Note: Setting this value to zero disables the delay timer interrupt.
Note: This field is ignored when AXI DMA is configured for Direct Register Mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="MM2S_DMASR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Status Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x04"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
+ <FIELDS>
+ <FIELD NAME="Halted">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Idle">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete. 1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="SGIncld">
+ <PROPERTY NAME="DESCRIPTION" VALUE="1 - Scatter Gather Enabled
0 - Scatter Gather not enabled
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="DMAIntErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected. DMA Engine halts
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="DMASlvErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected. DMA Engine halts
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="DMADecErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected. DMA Engine halts.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="SGIntErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit†already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="SGSlvErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="SGDecErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="IOC_Irq">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Dly_Irq">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Err_Irq">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
Writing a 1 to this bit will clear it. 
0 - No error Interrupt. 
1 - Error interrupt detected.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="IRQThresholdSts">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.
Note: Applicable only when Scatter Gather is enabled.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ <FIELD NAME="IRQDelaySts">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.
Note: Applicable only when Scatter Gather is enabled.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="MM2S_CURDESC">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Current_Descriptor_Pointer">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.
When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.
On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.
Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="MM2S_CURDESC_MSB">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Current_Descriptor_Pointer">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.
When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.
On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.
Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="MM2S_TAILDESC">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Tail_Descriptor_Pointer">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.
If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.
Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="MM2S_TAILDESC_MSB">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Tail_Descriptor_Pointer">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.
If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.
Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="MM2S_SA">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Source_Address">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="MM2S_SA_MSB">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Source_Address">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.
Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="MM2S_LENGTH">
+ <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Transfer Length Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Length">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="SG_CTL">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User and Cache Control Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x03"/>
+ <FIELDS>
+ <FIELD NAME="SG_CACHE">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+ </FIELD>
+ <FIELD NAME="SG_USER">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_DMACR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Control Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x30"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
+ <FIELDS>
+ <FIELD NAME="RS">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.
 0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. 
 AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.
 For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.
 The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.
 1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Reset">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.
AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State. 0 - Reset not in progress. Normal operation. 1 - Reset in progress
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Keyhole">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.
This bit is non functional when DMA is used in multichannel mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Cyclic_BD_Enable">
+ <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.
This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="IOC_IrqEn">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set. 0 - IOC Interrupt disabled 1 - IOC Interrupt enabled
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Dly_IrqEn">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Delay Interrupt disabled 1 - Delay Interrupt enabled Note: Applicable only when Scatter Gather is enabled.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Err_IrqEn">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out. 0 - Error Interrupt disabled 1 - Error Interrupt enabled
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="IRQThreshold">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.
Note: Applicable only when Scatter Gather is enabled.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ <FIELD NAME="IRQDelay">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.
Note: Setting this value to zero disables the delay timer interrupt.
Note: Applicable only when Scatter Gather is enabled.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_DMASR">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Status Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x34"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
+ <FIELDS>
+ <FIELD NAME="Halted">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel. 0 - DMA channel running. 1 - DMA channel halted. For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 
Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Idle">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.
For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.
For Direct Register Mode when IDLE indicates the current transfer has completed. 0 - Not Idle. 1 - Idle. Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="SGIncld">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="DMAIntErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.
This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Internal Errors 1 - DMA Internal Error detected.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="DMASlvErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Slave Errors. 1 - DMA Slave Error detected.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="DMADecErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No DMA Decode Errors. 1 - DMA Decode Error detected.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="SGIntErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit†already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Internal Errors. 1 - SG Internal Error detected. Note: Applicable only when Scatter Gather is enabled. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="SGSlvErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Slave Errors. 1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="SGDecErr">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1. 0 - No SG Decode Errors. 1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="IOC_Irq">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA. 0 - No IOC Interrupt. 1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Dly_Irq">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA. 0 - No Delay Interrupt. 1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="Err_Irq">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.
Writing a 1 to this bit will clear it. 0 - No error Interrupt. 1 - Error interrupt detected.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
+ </FIELD>
+ <FIELD NAME="IRQThresholdSts">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.
Note: Applicable only when Scatter Gather is enabled.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ <FIELD NAME="IRQDelaySts">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.
Note: Applicable only when Scatter Gather is enabled.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-only"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_CURDESC">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x38"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Current_Descriptor_Pointer">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.
When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.
On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.
Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). 
Buffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_CURDESC_MSB">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x3C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Current_Descriptor_Pointer">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.
When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.
On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.
Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_TAILDESC">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Tail_Descriptor_Pointer">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.
If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.
Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. 
Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_TAILDESC_MSB">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x44"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Tail_Descriptor_Pointer">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.
If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.
Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_DA">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Destination Address Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x48"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Destination_Address">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_DA_MSB">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM Destination Address Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4C"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Destination_Address">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.
Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ <REGISTER NAME="S2MM_LENGTH">
+ <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Transfer Length Register"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x58"/>
+ <PROPERTY NAME="SIZE" VALUE="32"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
+ <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
+ <FIELDS>
+ <FIELD NAME="Length">
+ <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.
At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. 
"/>
+ <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="ACCESS" VALUE="read-write"/>
+ <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
+ <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
+ <PROPERTY NAME="READ_ACTION" VALUE=""/>
+ <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
+ <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
+ </FIELD>
+ </FIELDS>
+ </REGISTER>
+ </REGISTERS>
+ </ADDRESSBLOCK>
+ </ADDRESSBLOCKS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_S_AXI_LITE_ADDR_WIDTH" VALUE="10"/>
+ <PARAMETER NAME="C_S_AXI_LITE_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_DLYTMR_RESOLUTION" VALUE="125"/>
+ <PARAMETER NAME="C_PRMRY_IS_ACLK_ASYNC" VALUE="0"/>
+ <PARAMETER NAME="C_ENABLE_MULTI_CHANNEL" VALUE="0"/>
+ <PARAMETER NAME="C_NUM_MM2S_CHANNELS" VALUE="1"/>
+ <PARAMETER NAME="C_NUM_S2MM_CHANNELS" VALUE="1"/>
+ <PARAMETER NAME="C_INCLUDE_SG" VALUE="0"/>
+ <PARAMETER NAME="C_SG_INCLUDE_STSCNTRL_STRM" VALUE="0"/>
+ <PARAMETER NAME="C_SG_USE_STSAPP_LENGTH" VALUE="0"/>
+ <PARAMETER NAME="C_SG_LENGTH_WIDTH" VALUE="26"/>
+ <PARAMETER NAME="C_M_AXI_SG_ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_M_AXI_SG_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_MICRO_DMA" VALUE="0"/>
+ <PARAMETER NAME="C_INCLUDE_MM2S" VALUE="1"/>
+ <PARAMETER NAME="C_INCLUDE_MM2S_SF" VALUE="1"/>
+ <PARAMETER NAME="C_MM2S_BURST_SIZE" VALUE="16"/>
+ <PARAMETER NAME="C_M_AXI_MM2S_ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_M_AXI_MM2S_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_M_AXIS_MM2S_TDATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_INCLUDE_MM2S_DRE" VALUE="0"/>
+ <PARAMETER NAME="C_INCLUDE_S2MM" VALUE="1"/>
+ <PARAMETER NAME="C_INCLUDE_S2MM_SF" VALUE="1"/>
+ <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="16"/>
+ <PARAMETER NAME="C_M_AXI_S2MM_ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_M_AXI_S2MM_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_S_AXIS_S2MM_TDATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_INCLUDE_S2MM_DRE" VALUE="0"/>
+ <PARAMETER NAME="C_INCREASE_THROUGHPUT" VALUE="0"/>
+ <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_axi_dma_0_0"/>
+ <PARAMETER NAME="c_include_sg" VALUE="0"/>
+ <PARAMETER NAME="c_enable_multi_channel" VALUE="0"/>
+ <PARAMETER NAME="c_num_mm2s_channels" VALUE="1"/>
+ <PARAMETER NAME="c_num_s2mm_channels" VALUE="1"/>
+ <PARAMETER NAME="c_sg_length_width" VALUE="26"/>
+ <PARAMETER NAME="c_dlytmr_resolution" VALUE="125"/>
+ <PARAMETER NAME="c_prmry_is_aclk_async" VALUE="0"/>
+ <PARAMETER NAME="c_sg_include_stscntrl_strm" VALUE="0"/>
+ <PARAMETER NAME="c_micro_dma" VALUE="0"/>
+ <PARAMETER NAME="c_include_mm2s" VALUE="1"/>
+ <PARAMETER NAME="c_m_axi_mm2s_data_width" VALUE="32"/>
+ <PARAMETER NAME="c_m_axis_mm2s_tdata_width" VALUE="32"/>
+ <PARAMETER NAME="c_include_mm2s_dre" VALUE="0"/>
+ <PARAMETER NAME="c_include_mm2s_sf" VALUE="1"/>
+ <PARAMETER NAME="c_mm2s_burst_size" VALUE="16"/>
+ <PARAMETER NAME="c_include_s2mm" VALUE="1"/>
+ <PARAMETER NAME="c_sg_use_stsapp_length" VALUE="0"/>
+ <PARAMETER NAME="c_m_axi_s2mm_data_width" VALUE="32"/>
+ <PARAMETER NAME="c_s_axis_s2mm_tdata_width" VALUE="32"/>
+ <PARAMETER NAME="c_include_s2mm_dre" VALUE="0"/>
+ <PARAMETER NAME="c_include_s2mm_sf" VALUE="1"/>
+ <PARAMETER NAME="c_s2mm_burst_size" VALUE="16"/>
+ <PARAMETER NAME="c_addr_width" VALUE="32"/>
+ <PARAMETER NAME="c_single_interface" VALUE="0"/>
+ <PARAMETER NAME="c_increase_throughput" VALUE="0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ <PARAMETER NAME="C_BASEADDR" VALUE="0x41E00000"/>
+ <PARAMETER NAME="C_HIGHADDR" VALUE="0x41E0FFFF"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT CLKFREQUENCY="50000000" DIR="I" NAME="s_axi_lite_aclk" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="50000000" DIR="I" NAME="m_axi_mm2s_aclk" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="50000000" DIR="I" NAME="m_axi_s2mm_aclk" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="axi_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="m_axi_mm2s_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="m_axi_mm2s_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="m_axi_mm2s_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="m_axi_mm2s_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="m_axi_mm2s_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="mm2s_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="din_TDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tkeep">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="din_TKEEP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="m_axis_mm2s_tvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="din_TVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="m_axis_mm2s_tready" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="din_TREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="m_axis_mm2s_tlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="din_TLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="m_axi_s2mm_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="m_axi_s2mm_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="m_axi_s2mm_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="m_axi_s2mm_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="m_axi_s2mm_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="m_axi_s2mm_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s2mm_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
+ <PORT DIR="I" LEFT="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="dout_TDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tkeep">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="dout_TKEEP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="dout_TVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="s_axis_s2mm_tready" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="dout_TREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="s_axis_s2mm_tlast" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="dout_TLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT"/>
+ <PORT DIR="O" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT"/>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="ps_axi_periph_M00_AXI" DATAWIDTH="32" NAME="S_AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="10"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="0"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_lite_araddr"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_lite_arready"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_lite_arvalid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_lite_awaddr"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_lite_awready"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_lite_awvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_lite_bready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_lite_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_lite_bvalid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_lite_rdata"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_lite_rready"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_lite_rresp"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_lite_rvalid"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_lite_wdata"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_lite_wready"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_lite_wvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_MM2S" DATAWIDTH="32" NAME="M_AXI_MM2S" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_ONLY"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="0"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="m_axi_mm2s_araddr"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="m_axi_mm2s_arburst"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="m_axi_mm2s_arcache"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="m_axi_mm2s_arlen"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="m_axi_mm2s_arprot"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="m_axi_mm2s_arready"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="m_axi_mm2s_arsize"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="m_axi_mm2s_arvalid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="m_axi_mm2s_rdata"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="m_axi_mm2s_rlast"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="m_axi_mm2s_rready"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="m_axi_mm2s_rresp"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="m_axi_mm2s_rvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_S2MM" DATAWIDTH="32" NAME="M_AXI_S2MM" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="0"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_s2mm_awaddr"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_s2mm_awburst"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_s2mm_awcache"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_s2mm_awlen"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_s2mm_awprot"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_s2mm_awready"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_s2mm_awsize"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_s2mm_awvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_s2mm_bready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_s2mm_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_s2mm_bvalid"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_s2mm_wdata"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_s2mm_wlast"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_s2mm_wready"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_s2mm_wstrb"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_s2mm_wvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXIS_MM2S" NAME="M_AXIS_MM2S" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
+ <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
+ <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+ <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+ <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+ <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_mm2s_tdata"/>
+ <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_mm2s_tkeep"/>
+ <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_mm2s_tlast"/>
+ <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_mm2s_tready"/>
+ <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_mm2s_tvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="pixel_dout" NAME="S_AXIS_S2MM" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
+ <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
+ <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+ <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
+ <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+ <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_s2mm_tdata"/>
+ <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_s2mm_tkeep"/>
+ <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_s2mm_tlast"/>
+ <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_s2mm_tready"/>
+ <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_s2mm_tvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ <MEMORYMAP>
+ <MEMRANGE ADDRESSBLOCK="HP0_DDR_LOWOCM" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="ps" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_MM2S" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0"/>
+ <MEMRANGE ADDRESSBLOCK="HP0_DDR_LOWOCM" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="ps" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0"/>
+ </MEMORYMAP>
+ <PERIPHERALS>
+ <PERIPHERAL INSTANCE="ps"/>
+ <PERIPHERAL INSTANCE="pixel"/>
+ </PERIPHERALS>
+ </MODULE>
+ <MODULE COREREVISION="23" FULLNAME="/axi_mem_intercon" HWVERSION="2.1" INSTANCE="axi_mem_intercon" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+ </DOCUMENTS>
+ <PARAMETERS>
+ <PARAMETER NAME="NUM_SI" VALUE="2"/>
+ <PARAMETER NAME="NUM_MI" VALUE="1"/>
+ <PARAMETER NAME="STRATEGY" VALUE="0"/>
+ <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+ <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+ <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+ <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+ <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+ <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
+ <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
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+ <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
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+ <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
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+ <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
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+ <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
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+ <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
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+ <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M00_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M01_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M02_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M03_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M04_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M05_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M06_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M07_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M08_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M09_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M10_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M11_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M12_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M13_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M14_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M15_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M16_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M17_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M18_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M19_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M20_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M21_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M22_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M23_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M24_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M25_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M26_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M27_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M28_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M29_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M30_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M31_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M32_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M33_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M34_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M35_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M36_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M37_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M38_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M39_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M40_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M41_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M42_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M43_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M44_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M45_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M46_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M47_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+ <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_axi_mem_intercon_0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S01_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S01_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_araddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rdata" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_AWREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="63" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="7" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WSTRB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="5" NAME="M00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="5" NAME="M00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="63" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WID"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_MM2S" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+ <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+ <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" DATAWIDTH="64" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWID" PHYSICAL="M00_AXI_awid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWREGION" PHYSICAL="M00_AXI_awregion"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
+ <PORTMAP LOGICAL="BID" PHYSICAL="M00_AXI_bid"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="M00_AXI_arid"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARREGION" PHYSICAL="M00_AXI_arregion"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
+ <PORTMAP LOGICAL="RID" PHYSICAL="M00_AXI_rid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+ <PORTMAP LOGICAL="WID" PHYSICAL="M00_AXI_wid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXI_S2MM" DATAWIDTH="32" NAME="S01_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="AWID" PHYSICAL="S01_AXI_awid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="S01_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="S01_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S01_AXI_awsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="S01_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S01_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S01_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="S01_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="S01_AXI_awqos"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="S01_AXI_awvalid"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="S01_AXI_awready"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="S01_AXI_wdata"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="S01_AXI_wstrb"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="S01_AXI_wlast"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="S01_AXI_wvalid"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="S01_AXI_wready"/>
+ <PORTMAP LOGICAL="BID" PHYSICAL="S01_AXI_bid"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="S01_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="S01_AXI_bvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="S01_AXI_bready"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="S01_AXI_arid"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="S01_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="S01_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S01_AXI_arsize"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="S01_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S01_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S01_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="S01_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="S01_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="S01_AXI_arvalid"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="S01_AXI_arready"/>
+ <PORTMAP LOGICAL="RID" PHYSICAL="S01_AXI_rid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="S01_AXI_rdata"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="S01_AXI_rresp"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="S01_AXI_rlast"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="S01_AXI_rvalid"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="S01_AXI_rready"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ </MODULE>
+ <MODULE COREREVISION="2105312237" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <DOCUMENTS/>
+ <PARAMETERS>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_pixel_0"/>
+ <PARAMETER NAME="clk_period" VALUE="10"/>
+ <PARAMETER NAME="machine" VALUE="64"/>
+ <PARAMETER NAME="combinational" VALUE="0"/>
+ <PARAMETER NAME="latency" VALUE="7"/>
+ <PARAMETER NAME="II" VALUE="x"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT CLKFREQUENCY="50000000" DIR="I" NAME="ap_clk" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="ap_rst_n" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="din_TVALID" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="din_TREADY" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="din_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="0" NAME="din_TLAST" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="din_TKEEP" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axis_mm2s_tkeep">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axis_mm2s_tkeep"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="din_TSTRB" RIGHT="0" SIGIS="undef"/>
+ <PORT DIR="O" NAME="dout_TVALID" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="dout_TREADY" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="dout_TDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="dout_TLAST" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="dout_TKEEP" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axis_s2mm_tkeep">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axis_s2mm_tkeep"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="dout_TSTRB" RIGHT="0" SIGIS="undef"/>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="axi_dma_0_M_AXIS_MM2S" NAME="din" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
+ <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
+ <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
+ <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+ <PARAMETER NAME="HAS_TSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+ <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="TVALID" PHYSICAL="din_TVALID"/>
+ <PORTMAP LOGICAL="TREADY" PHYSICAL="din_TREADY"/>
+ <PORTMAP LOGICAL="TDATA" PHYSICAL="din_TDATA"/>
+ <PORTMAP LOGICAL="TLAST" PHYSICAL="din_TLAST"/>
+ <PORTMAP LOGICAL="TKEEP" PHYSICAL="din_TKEEP"/>
+ <PORTMAP LOGICAL="TSTRB" PHYSICAL="din_TSTRB"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="pixel_dout" NAME="dout" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
+ <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
+ <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="LAYERED_METADATA"/>
+ <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
+ <PARAMETER NAME="HAS_TSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
+ <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="TVALID" PHYSICAL="dout_TVALID"/>
+ <PORTMAP LOGICAL="TREADY" PHYSICAL="dout_TREADY"/>
+ <PORTMAP LOGICAL="TDATA" PHYSICAL="dout_TDATA"/>
+ <PORTMAP LOGICAL="TLAST" PHYSICAL="dout_TLAST"/>
+ <PORTMAP LOGICAL="TKEEP" PHYSICAL="dout_TKEEP"/>
+ <PORTMAP LOGICAL="TSTRB" PHYSICAL="dout_TSTRB"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ </MODULE>
+ <MODULE CONFIGURABLE="TRUE" COREREVISION="6" FULLNAME="/ps" HWVERSION="5.5" INSTANCE="ps" IPTYPE="PERIPHERAL" IS_ENABLE="1" IS_PL="FALSE" MODTYPE="processing_system7" VLNV="xilinx.com:ip:processing_system7:5.5">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=processing_system7;v=v5_3;d=pg082-processing-system7.pdf"/>
+ </DOCUMENTS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_EN_EMIO_PJTAG" VALUE="0"/>
+ <PARAMETER NAME="C_EN_EMIO_ENET0" VALUE="0"/>
+ <PARAMETER NAME="C_EN_EMIO_ENET1" VALUE="0"/>
+ <PARAMETER NAME="C_EN_EMIO_TRACE" VALUE="0"/>
+ <PARAMETER NAME="C_INCLUDE_TRACE_BUFFER" VALUE="0"/>
+ <PARAMETER NAME="C_TRACE_BUFFER_FIFO_SIZE" VALUE="128"/>
+ <PARAMETER NAME="USE_TRACE_DATA_EDGE_DETECTOR" VALUE="0"/>
+ <PARAMETER NAME="C_TRACE_PIPELINE_WIDTH" VALUE="8"/>
+ <PARAMETER NAME="C_TRACE_BUFFER_CLOCK_DELAY" VALUE="12"/>
+ <PARAMETER NAME="C_EMIO_GPIO_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_INCLUDE_ACP_TRANS_CHECK" VALUE="0"/>
+ <PARAMETER NAME="C_USE_DEFAULT_ACP_USER_VAL" VALUE="0"/>
+ <PARAMETER NAME="C_S_AXI_ACP_ARUSER_VAL" VALUE="31"/>
+ <PARAMETER NAME="C_S_AXI_ACP_AWUSER_VAL" VALUE="31"/>
+ <PARAMETER NAME="C_M_AXI_GP0_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="C_M_AXI_GP0_ENABLE_STATIC_REMAP" VALUE="0"/>
+ <PARAMETER NAME="C_M_AXI_GP1_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="C_M_AXI_GP1_ENABLE_STATIC_REMAP" VALUE="0"/>
+ <PARAMETER NAME="C_S_AXI_GP0_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_GP1_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_ACP_ID_WIDTH" VALUE="3"/>
+ <PARAMETER NAME="C_S_AXI_HP0_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_HP0_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_S_AXI_HP1_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_HP1_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_S_AXI_HP2_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_HP2_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_S_AXI_HP3_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="C_S_AXI_HP3_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="C_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="C_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="C_NUM_F2P_INTR_INPUTS" VALUE="1"/>
+ <PARAMETER NAME="C_IRQ_F2P_MODE" VALUE="DIRECT"/>
+ <PARAMETER NAME="C_DQ_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="C_DQS_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="C_DM_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="C_MIO_PRIMITIVE" VALUE="54"/>
+ <PARAMETER NAME="C_TRACE_INTERNAL_WIDTH" VALUE="2"/>
+ <PARAMETER NAME="C_USE_AXI_NONSECURE" VALUE="0"/>
+ <PARAMETER NAME="C_USE_M_AXI_GP0" VALUE="1"/>
+ <PARAMETER NAME="C_USE_M_AXI_GP1" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_GP0" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_GP1" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_HP0" VALUE="1"/>
+ <PARAMETER NAME="C_USE_S_AXI_HP1" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_HP2" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_HP3" VALUE="0"/>
+ <PARAMETER NAME="C_USE_S_AXI_ACP" VALUE="0"/>
+ <PARAMETER NAME="C_PS7_SI_REV" VALUE="PRODUCTION"/>
+ <PARAMETER NAME="C_FCLK_CLK0_BUF" VALUE="TRUE"/>
+ <PARAMETER NAME="C_FCLK_CLK1_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="C_FCLK_CLK2_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="C_FCLK_CLK3_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="C_PACKAGE_NAME" VALUE="clg400"/>
+ <PARAMETER NAME="C_GP0_EN_MODIFIABLE_TXN" VALUE="1"/>
+ <PARAMETER NAME="C_GP1_EN_MODIFIABLE_TXN" VALUE="1"/>
+ <PARAMETER NAME="PCW_DDR_RAM_BASEADDR" VALUE="0x00100000"/>
+ <PARAMETER NAME="PCW_DDR_RAM_HIGHADDR" VALUE="0x1FFFFFFF"/>
+ <PARAMETER NAME="PCW_UART0_BASEADDR" VALUE="0xE0000000"/>
+ <PARAMETER NAME="PCW_UART0_HIGHADDR" VALUE="0xE0000FFF"/>
+ <PARAMETER NAME="PCW_UART1_BASEADDR" VALUE="0xE0001000"/>
+ <PARAMETER NAME="PCW_UART1_HIGHADDR" VALUE="0xE0001FFF"/>
+ <PARAMETER NAME="PCW_I2C0_BASEADDR" VALUE="0xE0004000"/>
+ <PARAMETER NAME="PCW_I2C0_HIGHADDR" VALUE="0xE0004FFF"/>
+ <PARAMETER NAME="PCW_I2C1_BASEADDR" VALUE="0xE0005000"/>
+ <PARAMETER NAME="PCW_I2C1_HIGHADDR" VALUE="0xE0005FFF"/>
+ <PARAMETER NAME="PCW_SPI0_BASEADDR" VALUE="0xE0006000"/>
+ <PARAMETER NAME="PCW_SPI0_HIGHADDR" VALUE="0xE0006FFF"/>
+ <PARAMETER NAME="PCW_SPI1_BASEADDR" VALUE="0xE0007000"/>
+ <PARAMETER NAME="PCW_SPI1_HIGHADDR" VALUE="0xE0007FFF"/>
+ <PARAMETER NAME="PCW_CAN0_BASEADDR" VALUE="0xE0008000"/>
+ <PARAMETER NAME="PCW_CAN0_HIGHADDR" VALUE="0xE0008FFF"/>
+ <PARAMETER NAME="PCW_CAN1_BASEADDR" VALUE="0xE0009000"/>
+ <PARAMETER NAME="PCW_CAN1_HIGHADDR" VALUE="0xE0009FFF"/>
+ <PARAMETER NAME="PCW_GPIO_BASEADDR" VALUE="0xE000A000"/>
+ <PARAMETER NAME="PCW_GPIO_HIGHADDR" VALUE="0xE000AFFF"/>
+ <PARAMETER NAME="PCW_ENET0_BASEADDR" VALUE="0xE000B000"/>
+ <PARAMETER NAME="PCW_ENET0_HIGHADDR" VALUE="0xE000BFFF"/>
+ <PARAMETER NAME="PCW_ENET1_BASEADDR" VALUE="0xE000C000"/>
+ <PARAMETER NAME="PCW_ENET1_HIGHADDR" VALUE="0xE000CFFF"/>
+ <PARAMETER NAME="PCW_SDIO0_BASEADDR" VALUE="0xE0100000"/>
+ <PARAMETER NAME="PCW_SDIO0_HIGHADDR" VALUE="0xE0100FFF"/>
+ <PARAMETER NAME="PCW_SDIO1_BASEADDR" VALUE="0xE0101000"/>
+ <PARAMETER NAME="PCW_SDIO1_HIGHADDR" VALUE="0xE0101FFF"/>
+ <PARAMETER NAME="PCW_USB0_BASEADDR" VALUE="0xE0102000"/>
+ <PARAMETER NAME="PCW_USB0_HIGHADDR" VALUE="0xE0102fff"/>
+ <PARAMETER NAME="PCW_USB1_BASEADDR" VALUE="0xE0103000"/>
+ <PARAMETER NAME="PCW_USB1_HIGHADDR" VALUE="0xE0103fff"/>
+ <PARAMETER NAME="PCW_TTC0_BASEADDR" VALUE="0xE0104000"/>
+ <PARAMETER NAME="PCW_TTC0_HIGHADDR" VALUE="0xE0104fff"/>
+ <PARAMETER NAME="PCW_TTC1_BASEADDR" VALUE="0xE0105000"/>
+ <PARAMETER NAME="PCW_TTC1_HIGHADDR" VALUE="0xE0105fff"/>
+ <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE"/>
+ <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="14"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="30.0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="105.056"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="66.904"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="89.1715"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="113.63"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="98.503"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="68.5855"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="90.295"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="103.977"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.4535"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.4535"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.4535"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.4535"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" VALUE="-0.025"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.014"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" VALUE="-0.009"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" VALUE="-0.033"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY0" VALUE="0.089"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY1" VALUE="0.075"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY2" VALUE="0.085"/>
+ <PARAMETER NAME="PCW_PACKAGE_DDR_BOARD_DELAY3" VALUE="0.092"/>
+ <PARAMETER NAME="PCW_CPU_CPU_6X4X_MAX_RANGE" VALUE="667"/>
+ <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333"/>
+ <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666"/>
+ <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159"/>
+ <PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200"/>
+ <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60"/>
+ <PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60"/>
+ <PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100"/>
+ <PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="-1"/>
+ <PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="-1"/>
+ <PARAMETER NAME="PCW_I2C_PERIPHERAL_FREQMHZ" VALUE="25"/>
+ <PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333"/>
+ <PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200"/>
+ <PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200"/>
+ <PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_ACT_APU_PERIPHERAL_FREQMHZ" VALUE="666.666687"/>
+ <PARAMETER NAME="PCW_UIPARAM_ACT_DDR_FREQ_MHZ" VALUE="533.333374"/>
+ <PARAMETER NAME="PCW_ACT_DCI_PERIPHERAL_FREQMHZ" VALUE="10.158730"/>
+ <PARAMETER NAME="PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_SMC_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_USB0_PERIPHERAL_FREQMHZ" VALUE="60"/>
+ <PARAMETER NAME="PCW_ACT_USB1_PERIPHERAL_FREQMHZ" VALUE="60"/>
+ <PARAMETER NAME="PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_UART_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_SPI_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_CAN_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
+ <PARAMETER NAME="PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" VALUE="23.8095"/>
+ <PARAMETER NAME="PCW_ACT_I2C_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_ACT_WDT_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC_PERIPHERAL_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+ <PARAMETER NAME="PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" VALUE="200.000000"/>
+ <PARAMETER NAME="PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50.000000"/>
+ <PARAMETER NAME="PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" VALUE="10.000000"/>
+ <PARAMETER NAME="PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="111.111115"/>
+ <PARAMETER NAME="PCW_CLK0_FREQ" VALUE="50000000"/>
+ <PARAMETER NAME="PCW_CLK1_FREQ" VALUE="10000000"/>
+ <PARAMETER NAME="PCW_CLK2_FREQ" VALUE="10000000"/>
+ <PARAMETER NAME="PCW_CLK3_FREQ" VALUE="10000000"/>
+ <PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0"/>
+ <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2"/>
+ <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2"/>
+ <PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="8"/>
+ <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="4"/>
+ <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1"/>
+ <PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15"/>
+ <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7"/>
+ <PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="8"/>
+ <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1"/>
+ <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40"/>
+ <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="48"/>
+ <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32"/>
+ <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333"/>
+ <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1600.000"/>
+ <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667"/>
+ <PARAMETER NAME="PCW_SMC_PERIPHERAL_VALID" VALUE="0"/>
+ <PARAMETER NAME="PCW_SDIO_PERIPHERAL_VALID" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI_PERIPHERAL_VALID" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_VALID" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART_PERIPHERAL_VALID" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_CAN0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_CAN1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_ENET0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_ENET1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_PTP_ENET0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_PTP_ENET1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_GPIO" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_I2C0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_I2C1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_PJTAG" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SDIO0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_CD_SDIO0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_WP_SDIO0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SDIO1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_CD_SDIO1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_WP_SDIO1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SPI0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SPI1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_UART0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_UART1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_MODEM_UART0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_MODEM_UART1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_TTC0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_TTC1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_WDT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_TRACE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1"/>
+ <PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="1"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_GP0_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_GP1_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_ACP_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_HP0_FREQMHZ" VALUE="50"/>
+ <PARAMETER NAME="PCW_S_AXI_HP1_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_HP2_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_S_AXI_HP3_FREQMHZ" VALUE="10"/>
+ <PARAMETER NAME="PCW_USE_DMA0" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DMA1" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DMA2" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DMA3" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_TRACE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_PIPELINE_WIDTH" VALUE="8"/>
+ <PARAMETER NAME="PCW_INCLUDE_TRACE_BUFFER" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_BUFFER_FIFO_SIZE" VALUE="128"/>
+ <PARAMETER NAME="PCW_USE_TRACE_DATA_EDGE_DETECTOR" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_BUFFER_CLOCK_DELAY" VALUE="12"/>
+ <PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0"/>
+ <PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="DISABLED"/>
+ <PARAMETER NAME="PCW_USE_DEBUG" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_CR_FABRIC" VALUE="1"/>
+ <PARAMETER NAME="PCW_USE_AXI_FABRIC_IDLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DDR_BYPASS" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_FABRIC_INTERRUPT" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_PROC_EVENT_BUS" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_EXPANDED_IOP" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_HIGH_OCM" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_PS_SLCR_REGISTERS" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_EXPANDED_PS_SLCR_REGISTERS" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_CORESIGHT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_EMIO_SRAM_INT" VALUE="0"/>
+ <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_GP0_NUM_WRITE_THREADS" VALUE="4"/>
+ <PARAMETER NAME="PCW_GP0_NUM_READ_THREADS" VALUE="4"/>
+ <PARAMETER NAME="PCW_GP1_NUM_WRITE_THREADS" VALUE="4"/>
+ <PARAMETER NAME="PCW_GP1_NUM_READ_THREADS" VALUE="4"/>
+ <PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200"/>
+ <PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200"/>
+ <PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="PCW_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="PCW_S_AXI_GP0_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_GP1_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_ACP_ID_WIDTH" VALUE="3"/>
+ <PARAMETER NAME="PCW_INCLUDE_ACP_TRANS_CHECK" VALUE="0"/>
+ <PARAMETER NAME="PCW_USE_DEFAULT_ACP_USER_VAL" VALUE="0"/>
+ <PARAMETER NAME="PCW_S_AXI_ACP_ARUSER_VAL" VALUE="31"/>
+ <PARAMETER NAME="PCW_S_AXI_ACP_AWUSER_VAL" VALUE="31"/>
+ <PARAMETER NAME="PCW_S_AXI_HP0_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_S_AXI_HP1_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_S_AXI_HP2_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_S_AXI_HP3_ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PCW_NUM_F2P_INTR_INPUTS" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_DDR" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_SMC" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_QSPI" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CAN0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CAN1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_ENET0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_ENET1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_GPIO" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_I2C0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_I2C1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_PJTAG" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_SDIO0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_SDIO1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_SPI0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_SPI1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_UART0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_UART1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_MODEM_UART0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_MODEM_UART1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_TTC0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_TTC1" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_WDT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_TRACE" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_USB0" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_USB1" VALUE="0"/>
+ <PARAMETER NAME="PCW_DQ_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PCW_DQS_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="PCW_DM_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="PCW_MIO_PRIMITIVE" VALUE="54"/>
+ <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_RST0_PORT" VALUE="1"/>
+ <PARAMETER NAME="PCW_EN_RST1_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_RST2_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_RST3_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLKTRIG0_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLKTRIG1_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLKTRIG2_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_EN_CLKTRIG3_PORT" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC_ABORT_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC2_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC3_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC4_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC5_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC6_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_DMAC7_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SMC_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_QSPI_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_CTI_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_GPIO_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_USB0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_ENET0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SDIO0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_I2C0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SPI0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_UART0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_CAN0_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_USB1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_ENET1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SDIO1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_I2C1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_SPI1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_UART1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_P2F_CAN1_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_IRQ_F2P_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT"/>
+ <PARAMETER NAME="PCW_CORE0_FIQ_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_CORE0_IRQ_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_CORE1_FIQ_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_CORE1_IRQ_INTR" VALUE="0"/>
+ <PARAMETER NAME="PCW_VALUE_SILVERSION" VALUE="3"/>
+ <PARAMETER NAME="PCW_GP0_EN_MODIFIABLE_TXN" VALUE="1"/>
+ <PARAMETER NAME="PCW_GP1_EN_MODIFIABLE_TXN" VALUE="1"/>
+ <PARAMETER NAME="PCW_IMPORT_BOARD_PRESET" VALUE="None"/>
+ <PARAMETER NAME="PCW_PERIPHERAL_BOARD_PRESET" VALUE="None"/>
+ <PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 3.3V"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J128M8 JP-125"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="8 Bits"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="1024 MBits"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0"/>
+ <PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)"/>
+ <PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2"/>
+ <PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15"/>
+ <PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2"/>
+ <PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2"/>
+ <PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps"/>
+ <PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL"/>
+ <PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL"/>
+ <PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External"/>
+ <PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External"/>
+ <PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External"/>
+ <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X"/>
+ <PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL"/>
+ <PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL"/>
+ <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low"/>
+ <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low"/>
+ <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low"/>
+ <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="<Select>"/>
+ <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="<Select>"/>
+ <PARAMETER NAME="preset" VALUE="None"/>
+ <PARAMETER NAME="PCW_UIPARAM_GENERATE_SUMMARY" VALUE="NA"/>
+ <PARAMETER NAME="PCW_MIO_TREE_PERIPHERALS" VALUE="unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"/>
+ <PARAMETER NAME="PCW_MIO_TREE_SIGNALS" VALUE="unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned"/>
+ <PARAMETER NAME="PCW_PS7_SI_REV" VALUE="PRODUCTION"/>
+ <PARAMETER NAME="PCW_FPGA_FCLK0_ENABLE" VALUE="1"/>
+ <PARAMETER NAME="PCW_FPGA_FCLK1_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_FPGA_FCLK2_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_FPGA_FCLK3_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11"/>
+ <PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T0" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T1" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T2" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T3" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T4" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T5" VALUE="NA"/>
+ <PARAMETER NAME="PCW_SMC_CYCLE_T6" VALUE="NA"/>
+ <PARAMETER NAME="PCW_PACKAGE_NAME" VALUE="clg400"/>
+ <PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_ps_0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ <PARAMETER NAME="C_BASEADDR" VALUE="0x00000000"/>
+ <PARAMETER NAME="C_HIGHADDR" VALUE="0x1FFFFFFF"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT DIR="O" NAME="M_AXI_GP0_ARVALID" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_AWVALID" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_BREADY" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_RREADY" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_WLAST" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_wlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M_AXI_GP0_WVALID" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_ARID" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_AWID" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="M_AXI_GP0_WID" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_wid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_ARLOCK" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arlock"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_AWLOCK" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awlock"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arqos"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awqos"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="50000000" DIR="I" NAME="M_AXI_GP0_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_ARREADY" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_AWREADY" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_BVALID" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_RLAST" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_RVALID" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M_AXI_GP0_WREADY" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="M_AXI_GP0_BID" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_bid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="M_AXI_GP0_RID" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_rid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M_AXI_GP0_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S_AXI_HP0_ARREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S_AXI_HP0_AWREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S_AXI_HP0_BVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S_AXI_HP0_RLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S_AXI_HP0_RVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S_AXI_HP0_WREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S_AXI_HP0_BRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S_AXI_HP0_RRESP" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="5" NAME="S_AXI_HP0_BID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="5" NAME="S_AXI_HP0_RID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="63" NAME="S_AXI_HP0_RDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="7" NAME="S_AXI_HP0_RCOUNT" RIGHT="0" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="7" NAME="S_AXI_HP0_WCOUNT" RIGHT="0" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="2" NAME="S_AXI_HP0_RACOUNT" RIGHT="0" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="5" NAME="S_AXI_HP0_WACOUNT" RIGHT="0" SIGIS="undef"/>
+ <PORT CLKFREQUENCY="50000000" DIR="I" NAME="S_AXI_HP0_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S_AXI_HP0_ARVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S_AXI_HP0_AWVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S_AXI_HP0_BREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S_AXI_HP0_RDISSUECAP1_EN" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S_AXI_HP0_RREADY" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S_AXI_HP0_WLAST" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S_AXI_HP0_WRISSUECAP1_EN" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S_AXI_HP0_WVALID" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S_AXI_HP0_ARBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S_AXI_HP0_ARLOCK" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlock">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arlock"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S_AXI_HP0_ARSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S_AXI_HP0_AWBURST" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S_AXI_HP0_AWLOCK" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlock">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awlock"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S_AXI_HP0_AWSIZE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S_AXI_HP0_ARPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S_AXI_HP0_AWPROT" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S_AXI_HP0_ARADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S_AXI_HP0_AWADDR" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_ARCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_ARLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_ARQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arqos">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arqos"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_AWCACHE" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_AWLEN" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S_AXI_HP0_AWQOS" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awqos">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awqos"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="5" NAME="S_AXI_HP0_ARID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_arid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_arid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="5" NAME="S_AXI_HP0_AWID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_awid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_awid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="5" NAME="S_AXI_HP0_WID" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="63" NAME="S_AXI_HP0_WDATA" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="7" NAME="S_AXI_HP0_WSTRB" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wstrb">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_AXI_wstrb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT CLKFREQUENCY="50000000" DIR="O" NAME="FCLK_CLK0" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ACLK"/>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_ACLK"/>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="slowest_sync_clk"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_aclk"/>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_ACLK"/>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="ACLK"/>
+ <CONNECTION INSTANCE="pixel" PORT="ap_clk"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_aclk"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ACLK"/>
+ <CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_ACLK"/>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ACLK"/>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="ACLK"/>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ACLK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="FCLK_RESET0_N" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="ps_FCLK_RESET0_N">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="ext_reset_in"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="53" NAME="MIO" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="FIXED_IO_mio"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_CAS_n" SIGIS="undef" SIGNAME="ps_DDR_CAS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_cas_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_CKE" SIGIS="undef" SIGNAME="ps_DDR_CKE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_cke"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_Clk_n" SIGIS="clk" SIGNAME="ps_DDR_Clk_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_ck_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_Clk" SIGIS="clk" SIGNAME="ps_DDR_Clk">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_ck_p"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_CS_n" SIGIS="undef" SIGNAME="ps_DDR_CS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_cs_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_DRSTB" SIGIS="rst" SIGNAME="ps_DDR_DRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_reset_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_ODT" SIGIS="undef" SIGNAME="ps_DDR_ODT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_odt"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_RAS_n" SIGIS="undef" SIGNAME="ps_DDR_RAS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_ras_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_WEB" SIGIS="undef" SIGNAME="ps_DDR_WEB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_we_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="2" NAME="DDR_BankAddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_BankAddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_ba"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="14" NAME="DDR_Addr" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_Addr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_addr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_VRN" SIGIS="undef" SIGNAME="ps_DDR_VRN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="FIXED_IO_ddr_vrn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="DDR_VRP" SIGIS="undef" SIGNAME="ps_DDR_VRP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="FIXED_IO_ddr_vrp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_DM" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DM">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_dm"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="31" NAME="DDR_DQ" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQ">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_dq"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_DQS_n" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQS_n">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_dqs_n"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" LEFT="3" NAME="DDR_DQS" RIGHT="0" SIGIS="undef" SIGNAME="ps_DDR_DQS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="DDR_dqs_p"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="PS_SRSTB" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="FIXED_IO_ps_srstb"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="PS_CLK" SIGIS="undef" SIGNAME="ps_PS_CLK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="FIXED_IO_ps_clk"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="PS_PORB" SIGIS="undef" SIGNAME="ps_PS_PORB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="overlay_imp" PORT="FIXED_IO_ps_porb"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="ps_DDR" DATAWIDTH="8" NAME="DDR" TYPE="INITIATOR" VLNV="xilinx.com:interface:ddrx:1.0">
+ <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+ <PARAMETER NAME="TIMEPERIOD_PS" VALUE="1250"/>
+ <PARAMETER NAME="MEMORY_TYPE" VALUE="COMPONENTS"/>
+ <PARAMETER NAME="MEMORY_PART"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="8"/>
+ <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
+ <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="true"/>
+ <PARAMETER NAME="SLOT" VALUE="Single"/>
+ <PARAMETER NAME="CUSTOM_PARTS"/>
+ <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
+ <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
+ <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="TDM"/>
+ <PARAMETER NAME="CAS_LATENCY" VALUE="11"/>
+ <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="11"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="CAS_N" PHYSICAL="DDR_CAS_n"/>
+ <PORTMAP LOGICAL="CKE" PHYSICAL="DDR_CKE"/>
+ <PORTMAP LOGICAL="CK_N" PHYSICAL="DDR_Clk_n"/>
+ <PORTMAP LOGICAL="CK_P" PHYSICAL="DDR_Clk"/>
+ <PORTMAP LOGICAL="CS_N" PHYSICAL="DDR_CS_n"/>
+ <PORTMAP LOGICAL="RESET_N" PHYSICAL="DDR_DRSTB"/>
+ <PORTMAP LOGICAL="ODT" PHYSICAL="DDR_ODT"/>
+ <PORTMAP LOGICAL="RAS_N" PHYSICAL="DDR_RAS_n"/>
+ <PORTMAP LOGICAL="WE_N" PHYSICAL="DDR_WEB"/>
+ <PORTMAP LOGICAL="BA" PHYSICAL="DDR_BankAddr"/>
+ <PORTMAP LOGICAL="ADDR" PHYSICAL="DDR_Addr"/>
+ <PORTMAP LOGICAL="DM" PHYSICAL="DDR_DM"/>
+ <PORTMAP LOGICAL="DQ" PHYSICAL="DDR_DQ"/>
+ <PORTMAP LOGICAL="DQS_N" PHYSICAL="DDR_DQS_n"/>
+ <PORTMAP LOGICAL="DQS_P" PHYSICAL="DDR_DQS"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="ps_FIXED_IO" NAME="FIXED_IO" TYPE="INITIATOR" VLNV="xilinx.com:display_processing_system7:fixedio:1.0">
+ <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="MIO" PHYSICAL="MIO"/>
+ <PORTMAP LOGICAL="DDR_VRN" PHYSICAL="DDR_VRN"/>
+ <PORTMAP LOGICAL="DDR_VRP" PHYSICAL="DDR_VRP"/>
+ <PORTMAP LOGICAL="PS_SRSTB" PHYSICAL="PS_SRSTB"/>
+ <PORTMAP LOGICAL="PS_CLK" PHYSICAL="PS_CLK"/>
+ <PORTMAP LOGICAL="PS_PORB" PHYSICAL="PS_PORB"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="__NOC__" NAME="S_AXI_HP0_FIFO_CTRL" TYPE="TARGET" VLNV="xilinx.com:display_processing_system7:hpstatusctrl:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="RCOUNT" PHYSICAL="S_AXI_HP0_RCOUNT"/>
+ <PORTMAP LOGICAL="WCOUNT" PHYSICAL="S_AXI_HP0_WCOUNT"/>
+ <PORTMAP LOGICAL="RACOUNT" PHYSICAL="S_AXI_HP0_RACOUNT"/>
+ <PORTMAP LOGICAL="WACOUNT" PHYSICAL="S_AXI_HP0_WACOUNT"/>
+ <PORTMAP LOGICAL="RDISSUECAPEN" PHYSICAL="S_AXI_HP0_RDISSUECAP1_EN"/>
+ <PORTMAP LOGICAL="WRISSUECAPEN" PHYSICAL="S_AXI_HP0_WRISSUECAP1_EN"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="ps_M_AXI_GP0" DATAWIDTH="32" NAME="M_AXI_GP0" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="12"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="1"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M_AXI_GP0_ARVALID"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="M_AXI_GP0_AWVALID"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M_AXI_GP0_BREADY"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M_AXI_GP0_RREADY"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="M_AXI_GP0_WLAST"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M_AXI_GP0_WVALID"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="M_AXI_GP0_ARID"/>
+ <PORTMAP LOGICAL="AWID" PHYSICAL="M_AXI_GP0_AWID"/>
+ <PORTMAP LOGICAL="WID" PHYSICAL="M_AXI_GP0_WID"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="M_AXI_GP0_ARBURST"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M_AXI_GP0_ARLOCK"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M_AXI_GP0_ARSIZE"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="M_AXI_GP0_AWBURST"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M_AXI_GP0_AWLOCK"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M_AXI_GP0_AWSIZE"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="M_AXI_GP0_ARPROT"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="M_AXI_GP0_AWPROT"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M_AXI_GP0_ARADDR"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="M_AXI_GP0_AWADDR"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M_AXI_GP0_WDATA"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M_AXI_GP0_ARCACHE"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="M_AXI_GP0_ARLEN"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="M_AXI_GP0_ARQOS"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M_AXI_GP0_AWCACHE"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="M_AXI_GP0_AWLEN"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="M_AXI_GP0_AWQOS"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="M_AXI_GP0_WSTRB"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M_AXI_GP0_ARREADY"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M_AXI_GP0_AWREADY"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="M_AXI_GP0_BVALID"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="M_AXI_GP0_RLAST"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="M_AXI_GP0_RVALID"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M_AXI_GP0_WREADY"/>
+ <PORTMAP LOGICAL="BID" PHYSICAL="M_AXI_GP0_BID"/>
+ <PORTMAP LOGICAL="RID" PHYSICAL="M_AXI_GP0_RID"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="M_AXI_GP0_BRESP"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="M_AXI_GP0_RRESP"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="M_AXI_GP0_RDATA"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="axi_mem_intercon_M00_AXI" DATAWIDTH="64" NAME="S_AXI_HP0" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
+ <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
+ <PARAMETER NAME="PROTOCOL" VALUE="AXI3"/>
+ <PARAMETER NAME="FREQ_HZ" VALUE="50000000"/>
+ <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
+ <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
+ <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
+ <PARAMETER NAME="HAS_BURST" VALUE="1"/>
+ <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
+ <PARAMETER NAME="HAS_PROT" VALUE="1"/>
+ <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
+ <PARAMETER NAME="HAS_QOS" VALUE="1"/>
+ <PARAMETER NAME="HAS_REGION" VALUE="0"/>
+ <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
+ <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
+ <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
+ <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
+ <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
+ <PARAMETER NAME="PHASE" VALUE="0.000"/>
+ <PARAMETER NAME="CLK_DOMAIN" VALUE="overlay_ps_0_FCLK_CLK0"/>
+ <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
+ <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
+ <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
+ <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="S_AXI_HP0_ARREADY"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="S_AXI_HP0_AWREADY"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="S_AXI_HP0_BVALID"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="S_AXI_HP0_RLAST"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="S_AXI_HP0_RVALID"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="S_AXI_HP0_WREADY"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="S_AXI_HP0_BRESP"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="S_AXI_HP0_RRESP"/>
+ <PORTMAP LOGICAL="BID" PHYSICAL="S_AXI_HP0_BID"/>
+ <PORTMAP LOGICAL="RID" PHYSICAL="S_AXI_HP0_RID"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="S_AXI_HP0_RDATA"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="S_AXI_HP0_ARVALID"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="S_AXI_HP0_AWVALID"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="S_AXI_HP0_BREADY"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="S_AXI_HP0_RREADY"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="S_AXI_HP0_WLAST"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="S_AXI_HP0_WVALID"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="S_AXI_HP0_ARBURST"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S_AXI_HP0_ARLOCK"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S_AXI_HP0_ARSIZE"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="S_AXI_HP0_AWBURST"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S_AXI_HP0_AWLOCK"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S_AXI_HP0_AWSIZE"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="S_AXI_HP0_ARPROT"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="S_AXI_HP0_AWPROT"/>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="S_AXI_HP0_ARADDR"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="S_AXI_HP0_AWADDR"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S_AXI_HP0_ARCACHE"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="S_AXI_HP0_ARLEN"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="S_AXI_HP0_ARQOS"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S_AXI_HP0_AWCACHE"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="S_AXI_HP0_AWLEN"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="S_AXI_HP0_AWQOS"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="S_AXI_HP0_ARID"/>
+ <PORTMAP LOGICAL="AWID" PHYSICAL="S_AXI_HP0_AWID"/>
+ <PORTMAP LOGICAL="WID" PHYSICAL="S_AXI_HP0_WID"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="S_AXI_HP0_WDATA"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="S_AXI_HP0_WSTRB"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ <MEMORYMAP>
+ <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0x41E00000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x41E0FFFF" INSTANCE="axi_dma_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
+ </MEMORYMAP>
+ <PERIPHERALS>
+ <PERIPHERAL INSTANCE="axi_dma_0"/>
+ </PERIPHERALS>
+ </MODULE>
+ <MODULE COREREVISION="23" FULLNAME="/ps_axi_periph" HWVERSION="2.1" INSTANCE="ps_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
+ </DOCUMENTS>
+ <PARAMETERS>
+ <PARAMETER NAME="NUM_SI" VALUE="1"/>
+ <PARAMETER NAME="NUM_MI" VALUE="1"/>
+ <PARAMETER NAME="STRATEGY" VALUE="0"/>
+ <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
+ <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
+ <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
+ <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
+ <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
+ <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
+ <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
+ <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
+ <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
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+ <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
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+ <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
+ <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
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+ <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
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+ <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
+ <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
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+ <PARAMETER NAME="M48_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M49_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M50_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M51_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M52_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M53_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M54_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M55_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M56_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M57_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M58_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M59_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M60_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M61_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M62_SECURE" VALUE="0"/>
+ <PARAMETER NAME="M63_SECURE" VALUE="0"/>
+ <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_ps_axi_periph_0"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWADDR"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RRESP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RRESP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WDATA">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WDATA"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WREADY"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WVALID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_ARSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWBURST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWBURST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWCACHE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWCACHE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLEN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLEN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWLOCK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWLOCK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWPROT">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWPROT"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWQOS">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWQOS"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWSIZE">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_AWSIZE"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_BID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_BID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="11" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_RLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="11" NAME="S00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WID">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WLAST">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WLAST"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_WSTRB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_WSTRB"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES>
+ <BUSINTERFACE BUSNAME="ps_M_AXI_GP0" DATAWIDTH="32" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
+ <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
+ <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
+ <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
+ <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
+ <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
+ <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
+ <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
+ <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
+ <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
+ <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
+ <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
+ <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
+ <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
+ <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
+ <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
+ <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
+ <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
+ <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
+ <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
+ <PORTMAP LOGICAL="WID" PHYSICAL="S00_AXI_wid"/>
+ <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
+ <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ <BUSINTERFACE BUSNAME="ps_axi_periph_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
+ <PORTMAPS>
+ <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
+ <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
+ <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
+ <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
+ <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
+ <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
+ <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
+ <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
+ <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
+ <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
+ <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
+ <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
+ <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
+ <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
+ <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
+ <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
+ </PORTMAPS>
+ </BUSINTERFACE>
+ </BUSINTERFACES>
+ </MODULE>
+ <MODULE COREREVISION="13" FULLNAME="/rst_ps_50M" HWVERSION="5.0" INSTANCE="rst_ps_50M" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
+ <DOCUMENTS>
+ <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
+ </DOCUMENTS>
+ <PARAMETERS>
+ <PARAMETER NAME="C_FAMILY" VALUE="zynq"/>
+ <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
+ <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
+ <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
+ <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
+ <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
+ <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
+ <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
+ <PARAMETER NAME="Component_Name" VALUE="overlay_rst_ps_50M_0"/>
+ <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
+ <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
+ <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
+ </PARAMETERS>
+ <PORTS>
+ <PORT CLKFREQUENCY="50000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="ps_FCLK_CLK0">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_CLK0"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="ps_FCLK_RESET0_N">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="FCLK_RESET0_N"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
+ <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
+ <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
+ <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
+ <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_ps_50M_peripheral_aresetn">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="S00_ARESETN"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="M00_ARESETN"/>
+ <CONNECTION INSTANCE="ps_axi_periph" PORT="ARESETN"/>
+ <CONNECTION INSTANCE="pixel" PORT="ap_rst_n"/>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S00_ARESETN"/>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="M00_ARESETN"/>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="ARESETN"/>
+ <CONNECTION INSTANCE="axi_mem_intercon" PORT="S01_ARESETN"/>
+ </CONNECTIONS>
+ </PORT>
+ </PORTS>
+ <BUSINTERFACES/>
+ </MODULE>
+ </MODULES>
+
+</EDKSYSTEM>
diff --git a/rtl-proj/rtl.runs/impl_1/overlay.bit b/rtl-proj/rtl.runs/impl_1/overlay.bit
new file mode 100644
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literal 0
HcmV?d00001
--
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