diff --git a/overlay.bit b/overlay.bit
index 6222f8d0c7c43d8ec2b1e241c2f2a01acdf1cc9c..a5a468c232d51c932d3d70a542343b4967b01132 100644
Binary files a/overlay.bit and b/overlay.bit differ
diff --git a/overlay.hwh b/overlay.hwh
index 614d977676d2a07a98f8b3e74d9614af07fa80cd..19fd04b44be80b92b54f8bf4abfa11be5b9017a3 100644
--- a/overlay.hwh
+++ b/overlay.hwh
@@ -1,39 +1,9 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sat Jun 12 19:03:51 2021" VIVADOVERSION="2020.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sat Jun 12 21:22:18 2021" VIVADOVERSION="2020.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z020" NAME="overlay" PACKAGE="clg400" SPEEDGRADE="-1"/>
<EXTERNALPORTS>
- <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="MIO"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
- <CONNECTIONS>
- <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="IO" NAME="DDR_cas_n" SIGIS="undef" SIGNAME="ps_DDR_CAS_n">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="DDR_CAS_n"/>
@@ -109,6 +79,36 @@
<CONNECTION INSTANCE="ps" PORT="DDR_DQS"/>
</CONNECTIONS>
</PORT>
+ <PORT DIR="IO" LEFT="53" NAME="FIXED_IO_mio" RIGHT="0" SIGIS="undef" SIGNAME="ps_MIO">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="MIO"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrn" SIGIS="undef" SIGNAME="ps_DDR_VRN">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRN"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ddr_vrp" SIGIS="undef" SIGNAME="ps_DDR_VRP">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="DDR_VRP"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_srstb" SIGIS="undef" SIGNAME="ps_PS_SRSTB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_SRSTB"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_clk" SIGIS="undef" SIGNAME="ps_PS_CLK">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_CLK"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="IO" NAME="FIXED_IO_ps_porb" SIGIS="undef" SIGNAME="ps_PS_PORB">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="ps" PORT="PS_PORB"/>
+ </CONNECTIONS>
+ </PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
@@ -2099,95 +2099,6 @@
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_RREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
- <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
- <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
- <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
- <CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
- </CONNECTIONS>
- </PORT>
<PORT DIR="I" NAME="S01_AXI_awid" SIGIS="undef"/>
<PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_s2mm_awaddr">
<CONNECTIONS>
@@ -2289,6 +2200,95 @@
<PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef"/>
<PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef"/>
<PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awaddr" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wdata" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bid" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bresp" SIGIS="undef"/>
+ <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arid" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_araddr">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_araddr"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arlen">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arlen"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arsize">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arsize"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arburst">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arburst"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arcache">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arcache"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arprot">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arprot"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_arready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_arready"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rid" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="31" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rdata">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rdata"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rresp">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rresp"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rlast">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rlast"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rvalid">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rvalid"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_0_m_axi_mm2s_rready">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_mm2s_rready"/>
+ </CONNECTIONS>
+ </PORT>
<PORT DIR="O" LEFT="0" NAME="M00_AXI_wid" RIGHT="0" SIGIS="undef" SIGNAME="axi_mem_intercon_M00_AXI_wid">
<CONNECTIONS>
<CONNECTION INSTANCE="ps" PORT="S_AXI_HP0_WID"/>
@@ -2424,7 +2424,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
- <MODULE COREREVISION="2106121851" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
+ <MODULE COREREVISION="2106122109" FULLNAME="/pixel" HWVERSION="1.0" INSTANCE="pixel" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="pixel" VLNV="xilinx.com:hls:pixel:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi_control" NAME="Reg" RANGE="65536" USAGE="register">
@@ -4839,103 +4839,107 @@
<CONNECTION INSTANCE="rst_ps_50M" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
+ <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
+ <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
+ <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
+ <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
+ <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
+ <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
+ <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
+ <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
<CONNECTIONS>
- <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
+ </CONNECTIONS>
+ </PORT>
+ <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
+ <CONNECTIONS>
+ <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_AWADDR">
@@ -5103,107 +5107,103 @@
<CONNECTION INSTANCE="ps" PORT="M_AXI_GP0_RREADY"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWADDR">
- <CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWADDR"/>
- </CONNECTIONS>
- </PORT>
- <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWVALID">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awaddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awaddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_AWREADY">
+ <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_AWREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WDATA">
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_awready">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WDATA"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_awready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WSTRB">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WSTRB"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WVALID">
+ <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_WREADY">
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_wready">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_WREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_wready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BRESP">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BRESP"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BVALID">
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_BREADY">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_bready">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_BREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_bready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="31" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARADDR">
+ <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_araddr">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARADDR"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_araddr"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arprot" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
- <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARVALID">
+ <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
+ <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_ARREADY">
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_arready">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_ARREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_arready"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RDATA">
+ <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rdata">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RDATA"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rdata"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RRESP">
+ <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rresp">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RRESP"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rresp"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
- <PORT DIR="I" LEFT="0" NAME="M01_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RVALID">
+ <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
+ <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rvalid">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RVALID"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rvalid"/>
</CONNECTIONS>
</PORT>
- <PORT DIR="O" LEFT="0" NAME="M01_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="pixel_s_axi_control_RREADY">
+ <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_0_s_axi_lite_rready">
<CONNECTIONS>
- <CONNECTION INSTANCE="pixel" PORT="s_axi_control_RREADY"/>
+ <CONNECTION INSTANCE="axi_dma_0" PORT="s_axi_lite_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="11" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps_M_AXI_GP0_ARID">