Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version3064766
date_generatedFri Jun 4 02:07:50 2021 os_platformLIN64
product_versionVivado v2020.2 (64-bit) project_id1159f34b2cf7451aad26d8bd878b8ed1
project_iteration1 random_id21f7b7be3f6659d59816e2858c345004
registration_id21f7b7be3f6659d59816e2858c345004 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Xeon(R) CPU E5-2630 0 @ 2.30GHz cpu_speed1200.000 MHz
os_nameunknown os_releaseunknown
system_ram236.000 GB total_processors2

vivado_usage
other_data
guimode=1 tclmode=3
project_data
constraintsetcount=0 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=11 totalsynthesisruns=11

unisim_transformation
post_unisim_transformation
bibuf=130 bufg=1 carry4=101 fdce=69
fdpe=33 fdre=4265 fdse=122 gnd=175
lut1=162 lut2=491 lut3=1059 lut4=527
lut5=649 lut6=1053 ps7=1 ramb36e1=2
ramd32=26 rams32=8 srl16e=193 srlc32e=106
vcc=178
pre_unisim_transformation
bibuf=130 bufg=1 carry4=101 fdce=69
fdpe=33 fdre=4265 fdse=122 gnd=175
lut1=162 lut2=491 lut3=1059 lut4=527
lut5=649 lut6=1053 ps7=1 ram32m=4
ram32x1d=1 ramb36e1=2 srl16e=193 srlc32e=106
vcc=178

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=3 bram_ports_newly_gated=0 bram_ports_total=4 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=4075 srls_augmented=0
srls_newly_gated=0 srls_total=285

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA da_axi4_cnt=4 da_ps7_cnt=1
iptotal=1 maxhierdepth=0 numblks=18 numhdlrefblks=0
numhierblks=8 numhlsblks=1 numnonxlnxblks=0 numpkgbdblks=0
numreposblks=10 numsysgenblks=0 synth_mode=OOC_per_IP x_iplanguage=VERILOG
x_iplibrary=BlockDiagram x_ipname=overlay x_ipvendor=xilinx.com x_ipversion=1.00.a
axi_crossbar_v2_1_23_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=zynq
c_m_axi_addr_width=0x0000001000000010 c_m_axi_base_addr=0x00000000400000000000000041e00000 c_m_axi_read_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_read_issuing=0x0000000100000001
c_m_axi_secure=0x00000000 c_m_axi_write_connectivity=0xFFFFFFFFFFFFFFFF c_m_axi_write_issuing=0x0000000100000001 c_num_addr_ranges=1
c_num_master_slots=2 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=23
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2020.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_crossbar_v2_1_23_axi_crossbar/2
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=64 c_axi_id_width=1 c_axi_protocol=0 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=1 c_family=zynq
c_m_axi_addr_width=0x0000001d c_m_axi_base_addr=0x0000000000000000 c_m_axi_read_connectivity=0x00000001 c_m_axi_read_issuing=0x00000008
c_m_axi_secure=0x00000000 c_m_axi_write_connectivity=0x00000002 c_m_axi_write_issuing=0x00000008 c_num_addr_ranges=1
c_num_master_slots=1 c_num_slave_slots=2 c_r_register=0 c_s_axi_arb_priority=0x0000000000000000
c_s_axi_base_id=0x0000000100000000 c_s_axi_read_acceptance=0x0000000200000008 c_s_axi_single_thread=0x0000000000000000 c_s_axi_thread_id_width=0x0000000000000000
c_s_axi_write_acceptance=0x0000000800000002 core_container=NA iptotal=1 x_ipcorerevision=23
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2020.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_dma/1
c_dlytmr_resolution=125 c_enable_multi_channel=0 c_family=zynq c_include_mm2s=1
c_include_mm2s_dre=0 c_include_mm2s_sf=1 c_include_s2mm=1 c_include_s2mm_dre=0
c_include_s2mm_sf=1 c_include_sg=0 c_increase_throughput=0 c_m_axi_mm2s_addr_width=32
c_m_axi_mm2s_data_width=32 c_m_axi_s2mm_addr_width=32 c_m_axi_s2mm_data_width=32 c_m_axi_sg_addr_width=32
c_m_axi_sg_data_width=32 c_m_axis_mm2s_cntrl_tdata_width=32 c_m_axis_mm2s_tdata_width=32 c_micro_dma=0
c_mm2s_burst_size=16 c_num_mm2s_channels=1 c_num_s2mm_channels=1 c_prmry_is_aclk_async=0
c_s2mm_burst_size=16 c_s_axi_lite_addr_width=10 c_s_axi_lite_data_width=32 c_s_axis_s2mm_sts_tdata_width=32
c_s_axis_s2mm_tdata_width=32 c_sg_include_stscntrl_strm=0 c_sg_length_width=26 c_sg_use_stsapp_length=0
core_container=NA iptotal=1 x_ipcorerevision=23 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_dma x_ipproduct=Vivado 2020.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=7.1
axi_dwidth_converter_v2_1_22_top/1
c_axi_addr_width=32 c_axi_is_aclk_async=0 c_axi_protocol=0 c_axi_supports_read=1
c_axi_supports_write=0 c_family=zynq c_fifo_mode=0 c_m_axi_aclk_ratio=2
c_m_axi_data_width=64 c_max_split_beats=16 c_packing_level=1 c_s_axi_aclk_ratio=1
c_s_axi_data_width=32 c_s_axi_id_width=1 c_supports_id=0 c_synchronizer_stage=3
core_container=NA iptotal=1 x_ipcorerevision=22 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_dwidth_converter x_ipproduct=Vivado 2020.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.1
axi_dwidth_converter_v2_1_22_top/2
c_axi_addr_width=32 c_axi_is_aclk_async=0 c_axi_protocol=0 c_axi_supports_read=0
c_axi_supports_write=1 c_family=zynq c_fifo_mode=0 c_m_axi_aclk_ratio=2
c_m_axi_data_width=64 c_max_split_beats=16 c_packing_level=1 c_s_axi_aclk_ratio=1
c_s_axi_data_width=32 c_s_axi_id_width=1 c_supports_id=0 c_synchronizer_stage=3
core_container=NA iptotal=1 x_ipcorerevision=22 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_dwidth_converter x_ipproduct=Vivado 2020.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.1
axi_protocol_converter_v2_1_22_axi_protocol_converter/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=12 c_axi_ruser_width=1 c_axi_supports_read=1
c_axi_supports_user_signals=0 c_axi_supports_write=1 c_axi_wuser_width=1 c_family=zynq
c_ignore_id=0 c_m_axi_protocol=2 c_s_axi_protocol=1 c_translation_mode=2
core_container=NA iptotal=1 x_ipcorerevision=22 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_protocol_converter x_ipproduct=Vivado 2020.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.1
axi_protocol_converter_v2_1_22_axi_protocol_converter/2
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=64 c_axi_id_width=1 c_axi_ruser_width=1 c_axi_supports_read=1
c_axi_supports_user_signals=0 c_axi_supports_write=1 c_axi_wuser_width=1 c_family=zynq
c_ignore_id=0 c_m_axi_protocol=1 c_s_axi_protocol=0 c_translation_mode=2
core_container=NA iptotal=1 x_ipcorerevision=22 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_protocol_converter x_ipproduct=Vivado 2020.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.1
hls_ip_2020_2/1
core_container=NA hls_input_arch=others hls_input_clock=10.000000 hls_input_fixed=0
hls_input_float=0 hls_input_part=xc7z020-clg400-1 hls_input_type=cxx hls_syn_clock=6.723000
hls_syn_dsp=0 hls_syn_ff=146 hls_syn_lat=1 hls_syn_lut=357
hls_syn_mem=0 hls_syn_tpt=none hls_version=2020_2 iptotal=1
pixel/1
c_s_axi_control_addr_width=6 c_s_axi_control_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=2106040136 x_iplanguage=VERILOG x_iplibrary=hls x_ipname=pixel
x_ipproduct=Vivado 2020.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=0 c_ext_rst_width=4
c_family=zynq c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=13
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2020.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
processing_system7_v5.5_user_configuration/1
core_container=NA iptotal=1 pcw_apu_clk_ratio_enable=6:2:1 pcw_apu_peripheral_freqmhz=666.666666
pcw_armpll_ctrl_fbdiv=40 pcw_can0_grp_clk_enable=0 pcw_can0_peripheral_clksrc=External pcw_can0_peripheral_enable=0
pcw_can0_peripheral_freqmhz=-1 pcw_can1_grp_clk_enable=0 pcw_can1_peripheral_clksrc=External pcw_can1_peripheral_enable=0
pcw_can1_peripheral_freqmhz=-1 pcw_can_peripheral_clksrc=IO PLL pcw_can_peripheral_freqmhz=100 pcw_cpu_cpu_pll_freqmhz=1333.333
pcw_cpu_peripheral_clksrc=ARM PLL pcw_crystal_peripheral_freqmhz=33.333333 pcw_dci_peripheral_clksrc=DDR PLL pcw_dci_peripheral_freqmhz=10.159
pcw_ddr_ddr_pll_freqmhz=1066.667 pcw_ddr_hpr_to_critical_priority_level=15 pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32) pcw_ddr_lpr_to_critical_priority_level=2
pcw_ddr_peripheral_clksrc=DDR PLL pcw_ddr_port0_hpr_enable=0 pcw_ddr_port1_hpr_enable=0 pcw_ddr_port2_hpr_enable=0
pcw_ddr_port3_hpr_enable=0 pcw_ddr_write_to_critical_priority_level=2 pcw_ddrpll_ctrl_fbdiv=32 pcw_enet0_grp_mdio_enable=0
pcw_enet0_peripheral_clksrc=IO PLL pcw_enet0_peripheral_enable=0 pcw_enet0_peripheral_freqmhz=1000 Mbps pcw_enet0_reset_enable=0
pcw_enet1_grp_mdio_enable=0 pcw_enet1_peripheral_clksrc=IO PLL pcw_enet1_peripheral_enable=0 pcw_enet1_peripheral_freqmhz=1000 Mbps
pcw_enet1_reset_enable=0 pcw_enet_reset_polarity=Active Low pcw_fclk0_peripheral_clksrc=IO PLL pcw_fclk1_peripheral_clksrc=IO PLL
pcw_fclk2_peripheral_clksrc=IO PLL pcw_fclk3_peripheral_clksrc=IO PLL pcw_fpga0_peripheral_freqmhz=50 pcw_fpga1_peripheral_freqmhz=50
pcw_fpga2_peripheral_freqmhz=50 pcw_fpga3_peripheral_freqmhz=50 pcw_fpga_fclk0_enable=1 pcw_fpga_fclk1_enable=0
pcw_fpga_fclk2_enable=0 pcw_fpga_fclk3_enable=0 pcw_ftm_cti_in0=DISABLED pcw_ftm_cti_in1=DISABLED
pcw_ftm_cti_in2=DISABLED pcw_ftm_cti_in3=DISABLED pcw_ftm_cti_out0=DISABLED pcw_ftm_cti_out1=DISABLED
pcw_ftm_cti_out2=DISABLED pcw_ftm_cti_out3=DISABLED pcw_gpio_emio_gpio_enable=0 pcw_gpio_mio_gpio_enable=0
pcw_gpio_peripheral_enable=0 pcw_i2c0_grp_int_enable=0 pcw_i2c0_peripheral_enable=0 pcw_i2c0_reset_enable=0
pcw_i2c1_grp_int_enable=0 pcw_i2c1_peripheral_enable=0 pcw_i2c1_reset_enable=0 pcw_i2c_reset_polarity=Active Low
pcw_io_io_pll_freqmhz=1600.000 pcw_iopll_ctrl_fbdiv=48 pcw_irq_f2p_mode=DIRECT pcw_m_axi_gp0_freqmhz=50
pcw_m_axi_gp1_freqmhz=10 pcw_nand_cycles_t_ar=1 pcw_nand_cycles_t_clr=1 pcw_nand_cycles_t_rc=11
pcw_nand_cycles_t_rea=1 pcw_nand_cycles_t_rr=1 pcw_nand_cycles_t_wc=11 pcw_nand_cycles_t_wp=1
pcw_nand_grp_d8_enable=0 pcw_nand_peripheral_enable=0 pcw_nor_cs0_t_ceoe=1 pcw_nor_cs0_t_pc=1
pcw_nor_cs0_t_rc=11 pcw_nor_cs0_t_tr=1 pcw_nor_cs0_t_wc=11 pcw_nor_cs0_t_wp=1
pcw_nor_cs0_we_time=0 pcw_nor_cs1_t_ceoe=1 pcw_nor_cs1_t_pc=1 pcw_nor_cs1_t_rc=11
pcw_nor_cs1_t_tr=1 pcw_nor_cs1_t_wc=11 pcw_nor_cs1_t_wp=1 pcw_nor_cs1_we_time=0
pcw_nor_grp_a25_enable=0 pcw_nor_grp_cs0_enable=0 pcw_nor_grp_cs1_enable=0 pcw_nor_grp_sram_cs0_enable=0
pcw_nor_grp_sram_cs1_enable=0 pcw_nor_grp_sram_int_enable=0 pcw_nor_peripheral_enable=0 pcw_nor_sram_cs0_t_ceoe=1
pcw_nor_sram_cs0_t_pc=1 pcw_nor_sram_cs0_t_rc=11 pcw_nor_sram_cs0_t_tr=1 pcw_nor_sram_cs0_t_wc=11
pcw_nor_sram_cs0_t_wp=1 pcw_nor_sram_cs0_we_time=0 pcw_nor_sram_cs1_t_ceoe=1 pcw_nor_sram_cs1_t_pc=1
pcw_nor_sram_cs1_t_rc=11 pcw_nor_sram_cs1_t_tr=1 pcw_nor_sram_cs1_t_wc=11 pcw_nor_sram_cs1_t_wp=1
pcw_nor_sram_cs1_we_time=0 pcw_override_basic_clock=0 pcw_pcap_peripheral_clksrc=IO PLL pcw_pcap_peripheral_freqmhz=200
pcw_pjtag_peripheral_enable=0 pcw_preset_bank0_voltage=LVCMOS 3.3V pcw_preset_bank1_voltage=LVCMOS 3.3V pcw_qspi_grp_fbclk_enable=0
pcw_qspi_grp_io1_enable=0 pcw_qspi_grp_single_ss_enable=0 pcw_qspi_grp_ss1_enable=0 pcw_qspi_internal_highaddress=0xFCFFFFFF
pcw_qspi_peripheral_clksrc=IO PLL pcw_qspi_peripheral_enable=0 pcw_qspi_peripheral_freqmhz=200 pcw_s_axi_acp_freqmhz=10
pcw_s_axi_gp0_freqmhz=10 pcw_s_axi_gp1_freqmhz=10 pcw_s_axi_hp0_data_width=64 pcw_s_axi_hp0_freqmhz=50
pcw_s_axi_hp1_data_width=64 pcw_s_axi_hp1_freqmhz=10 pcw_s_axi_hp2_data_width=64 pcw_s_axi_hp2_freqmhz=10
pcw_s_axi_hp3_data_width=64 pcw_s_axi_hp3_freqmhz=10 pcw_sd0_grp_cd_enable=0 pcw_sd0_grp_pow_enable=0
pcw_sd0_grp_wp_enable=0 pcw_sd0_peripheral_enable=0 pcw_sd1_grp_cd_enable=0 pcw_sd1_grp_pow_enable=0
pcw_sd1_grp_wp_enable=0 pcw_sd1_peripheral_enable=0 pcw_sdio_peripheral_clksrc=IO PLL pcw_sdio_peripheral_freqmhz=100
pcw_smc_peripheral_clksrc=IO PLL pcw_smc_peripheral_freqmhz=100 pcw_spi0_grp_ss0_enable=0 pcw_spi0_grp_ss1_enable=0
pcw_spi0_grp_ss2_enable=0 pcw_spi0_peripheral_enable=0 pcw_spi1_grp_ss0_enable=0 pcw_spi1_grp_ss1_enable=0
pcw_spi1_grp_ss2_enable=0 pcw_spi1_peripheral_enable=0 pcw_spi_peripheral_clksrc=IO PLL pcw_spi_peripheral_freqmhz=166.666666
pcw_tpiu_peripheral_clksrc=External pcw_tpiu_peripheral_freqmhz=200 pcw_trace_grp_16bit_enable=0 pcw_trace_grp_2bit_enable=0
pcw_trace_grp_32bit_enable=0 pcw_trace_grp_4bit_enable=0 pcw_trace_grp_8bit_enable=0 pcw_trace_peripheral_enable=0
pcw_ttc0_clk0_peripheral_clksrc=CPU_1X pcw_ttc0_clk0_peripheral_freqmhz=133.333333 pcw_ttc0_clk1_peripheral_clksrc=CPU_1X pcw_ttc0_clk1_peripheral_freqmhz=133.333333
pcw_ttc0_clk2_peripheral_clksrc=CPU_1X pcw_ttc0_clk2_peripheral_freqmhz=133.333333 pcw_ttc0_peripheral_enable=0 pcw_ttc1_clk0_peripheral_clksrc=CPU_1X
pcw_ttc1_clk0_peripheral_freqmhz=133.333333 pcw_ttc1_clk1_peripheral_clksrc=CPU_1X pcw_ttc1_clk1_peripheral_freqmhz=133.333333 pcw_ttc1_clk2_peripheral_clksrc=CPU_1X
pcw_ttc1_clk2_peripheral_freqmhz=133.333333 pcw_ttc1_peripheral_enable=0 pcw_ttc_peripheral_freqmhz=50 pcw_uart0_baud_rate=115200
pcw_uart0_grp_full_enable=0 pcw_uart0_peripheral_enable=0 pcw_uart1_baud_rate=115200 pcw_uart1_grp_full_enable=0
pcw_uart1_peripheral_enable=0 pcw_uart_peripheral_clksrc=IO PLL pcw_uart_peripheral_freqmhz=100 pcw_uiparam_ddr_adv_enable=0
pcw_uiparam_ddr_al=0 pcw_uiparam_ddr_bank_addr_count=3 pcw_uiparam_ddr_bl=8 pcw_uiparam_ddr_board_delay0=0.25
pcw_uiparam_ddr_board_delay1=0.25 pcw_uiparam_ddr_board_delay2=0.25 pcw_uiparam_ddr_board_delay3=0.25 pcw_uiparam_ddr_bus_width=32 Bit
pcw_uiparam_ddr_cl=7 pcw_uiparam_ddr_clock_0_length_mm=0 pcw_uiparam_ddr_clock_0_package_length=80.4535 pcw_uiparam_ddr_clock_0_propogation_delay=160
pcw_uiparam_ddr_clock_1_length_mm=0 pcw_uiparam_ddr_clock_1_package_length=80.4535 pcw_uiparam_ddr_clock_1_propogation_delay=160 pcw_uiparam_ddr_clock_2_length_mm=0
pcw_uiparam_ddr_clock_2_package_length=80.4535 pcw_uiparam_ddr_clock_2_propogation_delay=160 pcw_uiparam_ddr_clock_3_length_mm=0 pcw_uiparam_ddr_clock_3_package_length=80.4535
pcw_uiparam_ddr_clock_3_propogation_delay=160 pcw_uiparam_ddr_clock_stop_en=0 pcw_uiparam_ddr_col_addr_count=10 pcw_uiparam_ddr_cwl=6
pcw_uiparam_ddr_device_capacity=1024 MBits pcw_uiparam_ddr_dq_0_length_mm=0 pcw_uiparam_ddr_dq_0_package_length=98.503 pcw_uiparam_ddr_dq_0_propogation_delay=160
pcw_uiparam_ddr_dq_1_length_mm=0 pcw_uiparam_ddr_dq_1_package_length=68.5855 pcw_uiparam_ddr_dq_1_propogation_delay=160 pcw_uiparam_ddr_dq_2_length_mm=0
pcw_uiparam_ddr_dq_2_package_length=90.295 pcw_uiparam_ddr_dq_2_propogation_delay=160 pcw_uiparam_ddr_dq_3_length_mm=0 pcw_uiparam_ddr_dq_3_package_length=103.977
pcw_uiparam_ddr_dq_3_propogation_delay=160 pcw_uiparam_ddr_dqs_0_length_mm=0 pcw_uiparam_ddr_dqs_0_package_length=105.056 pcw_uiparam_ddr_dqs_0_propogation_delay=160
pcw_uiparam_ddr_dqs_1_length_mm=0 pcw_uiparam_ddr_dqs_1_package_length=66.904 pcw_uiparam_ddr_dqs_1_propogation_delay=160 pcw_uiparam_ddr_dqs_2_length_mm=0
pcw_uiparam_ddr_dqs_2_package_length=89.1715 pcw_uiparam_ddr_dqs_2_propogation_delay=160 pcw_uiparam_ddr_dqs_3_length_mm=0 pcw_uiparam_ddr_dqs_3_package_length=113.63
pcw_uiparam_ddr_dqs_3_propogation_delay=160 pcw_uiparam_ddr_dqs_to_clk_delay_0=0.0 pcw_uiparam_ddr_dqs_to_clk_delay_1=0.0 pcw_uiparam_ddr_dqs_to_clk_delay_2=0.0
pcw_uiparam_ddr_dqs_to_clk_delay_3=0.0 pcw_uiparam_ddr_dram_width=8 Bits pcw_uiparam_ddr_ecc=Disabled pcw_uiparam_ddr_enable=1
pcw_uiparam_ddr_freq_mhz=533.333333 pcw_uiparam_ddr_high_temp=Normal (0-85) pcw_uiparam_ddr_memory_type=DDR 3 pcw_uiparam_ddr_partno=MT41J128M8 JP-125
pcw_uiparam_ddr_row_addr_count=14 pcw_uiparam_ddr_speed_bin=DDR3_1066F pcw_uiparam_ddr_t_faw=30.0 pcw_uiparam_ddr_t_ras_min=35.0
pcw_uiparam_ddr_t_rc=48.75 pcw_uiparam_ddr_t_rcd=7 pcw_uiparam_ddr_t_rp=7 pcw_uiparam_ddr_train_data_eye=1
pcw_uiparam_ddr_train_read_gate=1 pcw_uiparam_ddr_train_write_level=1 pcw_uiparam_ddr_use_internal_vref=0 pcw_usb0_peripheral_enable=0
pcw_usb0_peripheral_freqmhz=60 pcw_usb0_reset_enable=0 pcw_usb1_peripheral_enable=0 pcw_usb1_peripheral_freqmhz=60
pcw_usb1_reset_enable=0 pcw_usb_reset_polarity=Active Low pcw_use_cross_trigger=0 pcw_use_m_axi_gp0=1
pcw_use_m_axi_gp1=0 pcw_use_s_axi_acp=0 pcw_use_s_axi_gp0=0 pcw_use_s_axi_gp1=0
pcw_use_s_axi_hp0=1 pcw_use_s_axi_hp1=0 pcw_use_s_axi_hp2=0 pcw_use_s_axi_hp3=0
pcw_wdt_peripheral_clksrc=CPU_1X pcw_wdt_peripheral_enable=0 pcw_wdt_peripheral_freqmhz=133.333333
processing_system7_v5_5_processing_system7/1
c_dm_width=4 c_dq_width=32 c_dqs_width=4 c_emio_gpio_width=64
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_pjtag=0 c_en_emio_trace=0
c_fclk_clk0_buf=TRUE c_fclk_clk1_buf=FALSE c_fclk_clk2_buf=FALSE c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 c_gp1_en_modifiable_txn=1 c_include_acp_trans_check=0 c_include_trace_buffer=0
c_irq_f2p_mode=DIRECT c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp0_id_width=12 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_thread_id_width=12 c_mio_primitive=54
c_num_f2p_intr_inputs=1 c_package_name=clg400 c_ps7_si_rev=PRODUCTION c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 c_s_axi_acp_id_width=3 c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp0_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp2_id_width=6 c_s_axi_hp3_data_width=64 c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 c_trace_buffer_fifo_size=128 c_trace_internal_width=2 c_trace_pipeline_width=8
c_use_axi_nonsecure=0 c_use_default_acp_user_val=0 c_use_m_axi_gp0=1 c_use_m_axi_gp1=0
c_use_s_axi_acp=0 c_use_s_axi_gp0=0 c_use_s_axi_gp1=0 c_use_s_axi_hp0=1
c_use_s_axi_hp1=0 c_use_s_axi_hp2=0 c_use_s_axi_hp3=0 core_container=NA
iptotal=1 use_trace_data_edge_detector=0 x_ipcorerevision=6 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=processing_system7 x_ipproduct=Vivado 2020.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=5.5
xpm_cdc_async_rst/1
core_container=NA def_val=1'b0 dest_sync_ff=2 init_sync_ff=0
inv_def_val=1'b1 iptotal=3 rst_active_high=1 version=0
xpm_fifo_base/1
both_stages_valid=3 cascade_height=0 cdc_dest_sync_ff=2 common_clock=1
core_container=NA dout_reset_value=0 ecc_mode=0 en_adv_feature=16'b0001111100011111
en_ae=1'b1 en_af=1'b1 en_dvld=1'b1 en_of=1'b1
en_pe=1'b1 en_pf=1'b1 en_rdc=1'b1 en_uf=1'b1
en_wack=1'b1 en_wdc=1'b1 enable_ecc=0 fg_eq_asym_dout=1'b0
fifo_mem_type=0 fifo_memory_type=0 fifo_read_depth=16 fifo_read_latency=0
fifo_size=144 fifo_write_depth=16 full_reset_value=1 full_rst_val=1'b1
invalid=0 iptotal=3 pe_thresh_adj=8 pe_thresh_max=11
pe_thresh_min=5 pf_thresh_adj=8 pf_thresh_max=11 pf_thresh_min=5
prog_empty_thresh=10 prog_full_thresh=10 rd_data_count_width=4 rd_dc_width_ext=5
rd_latency=2 rd_mode=1 rd_pntr_width=4 read_data_width=9
read_mode=1 read_mode_ll=1 related_clocks=0 remove_wr_rd_prot_logic=0
sim_assert_chk=0 stage1_valid=2 stage2_valid=1 use_adv_features=1F1F
version=0 wakeup_time=0 width_ratio=1 wr_data_count_width=5
wr_dc_width_ext=5 wr_depth_log=4 wr_pntr_width=4 wr_rd_ratio=0
wr_width_log=4 write_data_width=9
xpm_fifo_sync/1
cascade_height=0 core_container=NA dout_reset_value=0 ecc_mode=no_ecc
en_adv_feature_sync=16'b0001111100011111 fifo_memory_type=auto fifo_read_latency=0 fifo_write_depth=16
full_reset_value=1 iptotal=3 p_common_clock=1 p_ecc_mode=0
p_fifo_memory_type=0 p_read_mode=1 p_wakeup_time=2 prog_empty_thresh=10
prog_full_thresh=10 rd_data_count_width=4 read_data_width=9 read_mode=fwft
sim_assert_chk=0 use_adv_features=1F1F wakeup_time=0 wr_data_count_width=5
write_data_width=9
xpm_memory_base/1
write_data_width=9 addr_width_a=4 addr_width_b=4 auto_sleep_time=0
byte_write_width_a=9 byte_write_width_b=9 cascade_height=0 clocking_mode=0
core_container=NA ecc_mode=0 iptotal=3 max_num_char=0
memory_optimization=true memory_primitive=0 memory_size=144 memory_type=1
message_control=0 num_char_loc=0 p_ecc_mode=no_ecc p_enable_byte_write_a=0
p_enable_byte_write_b=0 p_max_depth_data=16 p_memory_opt=yes p_memory_primitive=auto
p_min_width_data=9 p_min_width_data_a=9 p_min_width_data_b=9 p_min_width_data_ecc=9
p_min_width_data_ldw=4 p_min_width_data_shft=9 p_num_cols_write_a=1 p_num_cols_write_b=1
p_num_rows_read_a=1 p_num_rows_read_b=1 p_num_rows_write_a=1 p_num_rows_write_b=1
p_sdp_write_mode=yes p_width_addr_lsb_read_a=0 p_width_addr_lsb_read_b=0 p_width_addr_lsb_write_a=0
p_width_addr_lsb_write_b=0 p_width_addr_read_a=4 p_width_addr_read_b=4 p_width_addr_write_a=4
p_width_addr_write_b=4 p_width_col_write_a=9 p_width_col_write_b=9 read_data_width_a=9
read_data_width_b=9 read_latency_a=2 read_latency_b=2 read_reset_value_a=0
read_reset_value_b=0 rst_mode_a=SYNC rst_mode_b=SYNC rsta_loop_iter=12
rstb_loop_iter=12 sim_assert_chk=0 use_embedded_constraint=0 use_mem_init=0
use_mem_init_mmi=0 version=0 wakeup_time=0 write_data_width_a=9
write_data_width_b=9 write_mode_a=2 write_mode_b=2 write_protect=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
reqp-181=2 rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
lutar-1=3

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") bram=0.000048 clocks=0.007783
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=High confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.136176 die=xc7z020clg400-1 dsp_output_toggle=12.500000 dynamic=1.537895
effective_thetaja=11.53 enable_probability=0.990000 family=zynq ff_toggle=12.500000
flow_state=routed heatsink=none input_toggle=12.500000 junction_temp=44.3 (C)
logic=0.001146 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=1.674070
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=clg400
pct_clock_constrained=6.480000 pct_inputs_defined=0 platform=lin64 process=typical
ps7=1.527332 ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.001586 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=7.4 (C/W)
thetasa=0.0 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=11.53
user_junc_temp=44.3 (C) user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000000
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.015149 vccaux_total_current=0.015149 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000001
vccbram_static_current=0.001026 vccbram_total_current=0.001027 vccbram_voltage=1.000000 vccint_dynamic_current=0.010561
vccint_static_current=0.014849 vccint_total_current=0.025411 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000000
vcco33_static_current=0.000000 vcco33_total_current=0.000000 vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.456904
vcco_ddr_static_current=0.002000 vcco_ddr_total_current=0.458904 vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000
vcco_mio0_static_current=0.000000 vcco_mio0_total_current=0.000000 vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000
vcco_mio1_static_current=0.000000 vcco_mio1_total_current=0.000000 vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.050131
vccpaux_static_current=0.010330 vccpaux_total_current=0.060461 vccpaux_voltage=1.800000 vccpint_dynamic_current=0.723985
vccpint_static_current=0.030037 vccpint_total_current=0.754023 vccpint_voltage=1.000000 vccpll_dynamic_current=0.015420
vccpll_static_current=0.003000 vccpll_total_current=0.018420 vccpll_voltage=1.800000 version=2020.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=1 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=1 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=2 block_ram_tile_util_percentage=1.43
ramb18_available=280 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=2 ramb36_fifo_util_percentage=1.43
ramb36e1_only_used=2
primitives
bibuf_functional_category=IO bibuf_used=130 bufg_functional_category=Clock bufg_used=1
carry4_functional_category=CarryLogic carry4_used=93 fdce_functional_category=Flop & Latch fdce_used=69
fdpe_functional_category=Flop & Latch fdpe_used=33 fdre_functional_category=Flop & Latch fdre_used=3852
fdse_functional_category=Flop & Latch fdse_used=121 lut1_functional_category=LUT lut1_used=86
lut2_functional_category=LUT lut2_used=466 lut3_functional_category=LUT lut3_used=1004
lut4_functional_category=LUT lut4_used=615 lut5_functional_category=LUT lut5_used=584
lut6_functional_category=LUT lut6_used=790 ps7_functional_category=Specialized Resource ps7_used=1
ramb36e1_functional_category=Block Memory ramb36e1_used=2 ramd32_functional_category=Distributed Memory ramd32_used=26
rams32_functional_category=Distributed Memory rams32_used=8 srl16e_functional_category=Distributed Memory srl16e_used=196
srlc32e_functional_category=Distributed Memory srlc32e_used=89
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=18 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=2762 lut_as_logic_util_percentage=5.19 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=223 lut_as_memory_util_percentage=1.28 lut_as_shift_register_fixed=0 lut_as_shift_register_used=205
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=4075 register_as_flip_flop_util_percentage=3.83
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=2985 slice_luts_util_percentage=5.61
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=4075 slice_registers_util_percentage=3.83
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=18 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=2762 lut_as_logic_util_percentage=5.19 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=223 lut_as_memory_util_percentage=1.28 lut_as_shift_register_fixed=0 lut_as_shift_register_used=205
lut_in_front_of_the_register_is_unused_fixed=205 lut_in_front_of_the_register_is_unused_used=1372 lut_in_front_of_the_register_is_used_fixed=1372 lut_in_front_of_the_register_is_used_used=404
register_driven_from_outside_the_slice_fixed=404 register_driven_from_outside_the_slice_used=1776 register_driven_from_within_the_slice_fixed=1776 register_driven_from_within_the_slice_used=2299
slice_available=13300 slice_fixed=0 slice_registers_available=106400 slice_registers_fixed=0
slice_registers_used=4075 slice_registers_util_percentage=3.83 slice_used=1342 slice_util_percentage=10.09
slicel_fixed=0 slicel_used=820 slicem_fixed=0 slicem_used=522
unique_control_sets_available=13300 unique_control_sets_fixed=13300 unique_control_sets_used=212 unique_control_sets_util_percentage=1.59
using_o5_and_o6_fixed=1.59 using_o5_and_o6_used=80 using_o5_output_only_fixed=80 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=125
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified] -max_bram=default::-1
-max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1
-mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified]
-no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7z020clg400-1 -resource_sharing=default::auto
-retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified]
-seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3 -top=overlay
-verilog_define=default::[not_specified]
usage
elapsed=00:00:34s hls_ip=0 memory_gain=64.031MB memory_peak=2352.094MB