# FPGA_final_project
#### Sabyasachi Mondal , Ravi Yadav
fpga vs cpu performance comparison and fpga streamlining for computation intensive tasks

# Overview
We want to use FPGA for implementing an algorithm in hardware to perform computation more effeciently. CPU hardware is non-flexible so the code runs using the same set of registers and ALU , we cant optimize the harware as per our code. Our objective here is to harware a processing unit (something smilar to a flexible ALU using the CLBs) in the FPGA using High level code.


# Background
CPUs are known for their general purpose use, the same GPUs can power all kinds of applications. EINAC the first computer in a sense had programmable cards, taking days to reprogram but used general purpose computations, the limitation is code could be used to perform any tasks. CPU can run simulate any finite state machine but can't be reprogrammed as a hardware. 

For application specific needs like signal processing wiring a device to do particular computations can prove much more efficient. We may implement an multiplier on the hardware level if we want. Depending on the kind of data we are can implement an hardware that can entirely process the exact type of data much faster. In CPU the hardware is static so all data will get converted to the same set of specific instruction set that runs one at a time in CPU.

If we know we will be doing a matrix addition for 2 4x4 array we can simply implement a register to register connected adder that will always give us the result of addition in the next cycle the data is received. In CPU we cant simply do that!

In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to compute :
1. *The weight matrix of a neural network* [Future Application to develop a hardware optimized neural network]

and 
compare how CPU performs in comparision to our FPGA hardware that is exactly wired up to work on the kind of data we expect to provide as input.

# Implementation Strategy
First we need to determine the type of data we would be using in our project. Based on that we need to decide the type of ports and hardware we can use in FPGA.

After this we need to determine a mental sketch of the hardware that if implemented can make the processing faster.

###### At this point we will do a project estimate analysis and select one of the above problem statement if needed (to fit within the time)

Next we need to know what high level functions transfer to which hardware component and write the code as per the hardware architechture we define in previous step.

After this we are goingto use the HLS tool Vitis to desgin and then use Vivado to generate our harware programmable bitstream for us, this bitstream configured will be used to process our data. We will be using python APIs to interact with our bitstream.

Next we implement the same algorithm in our python code that will obviously run on the cpu.

Then finally we can check the runtime and reach a conclusion on which is faster and why.

# Tasks
The Tasks and maximum estimated time:

1. Problem statement and solution Plan brainstorming and refresher on NN : *12 hrs*
2. Implementing the network in python CPU : *16 hrs*
3. Pseudo code and solution adjustment : *6 hrs*
4. Vivado study of other solutions, available tools, code and hardware correlation : *16 hrs*
5. Writting the code in Vivado : *6 hrs*
6. Implementing code and checking hardware features and making final adjustments : *16 hrs*
7. Bitstream generation python code for overlay : *2 hrs*
8. Drafting the report and Analysis : *4 hrs*


# Resources used and Future project topics
##### Resources used
Operation with stream: https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_stream_library.html#ivv1539734234667__ad398476
Specialized Constructs : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/special_graph_constructs.html?hl=template
Database in FPGA : https://dspace.mit.edu/bitstream/handle/1721.1/91829/894228451-MIT.pdf?sequence=2&isAllowed=y
Database in FPGA : https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/accelerating-databases-with-fpgas.pdf
Database in FPGA  : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_process.html#djn1584047476918
Vitis Examples : https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/cpp_kernels/README.md
Running Accelerator : https://pynq.readthedocs.io/en/v2.6.1/pynq_alveo.html#running-accelerators
Pragma Interfaces : https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/jit1504034365862.html
Interface of Streaming : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/managing_interface_synthesis.html#ariaid-title34
##### Future topics
A great resource for 32x32 image dataset: http://chaladze.com/l5/
Book to jumstart or serve as refresher: Programming Machine Learning (Perrotta, Paolo) [ISBN: , 9781680507720]
Hardware based Neural networks : https://users.ece.cmu.edu/~pgrover/teaching/files/NeuromorphicComputing.pdf
https://www.amiq.com/consulting/2018/12/14/how-to-implement-a-convolutional-neural-network-using-high-level-synthesis/
https://wiki.nus.edu.sg/display/ee4218/Hardware+Implementation+Flow

# Errors Logs and Issues encountered
 [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/color_filter/ap_start
When ap_Ctrl = None not specified in design

Cant find custom IP in Vivado : add IP zip path, open IP Integrator view, from IP configure window manually add the IP

Cant connect hls::stream<> type object in IP : Note: The hls::stream class should always be passed between functions as a C++ reference argument. For example, &my_stream.
IMPORTANT: The hls::stream class is only used in C++ designs. Array of streams is not supported.

Non-Blocking write not-allowed in Non-FIFO Interfaces like axis instead try using FIFO m_axi