Update README.md for Beta version

README.md

@@ -22,8 +22,10 @@ Our Objective is to develop better integrated code such that our hardware and so
 In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to perform image processing (like inversion, color specific background sieve) at a much faster rate:
 
 1. *Perform Image processing by using the registers, axi_streaming and DMA* [Future scope multi-agent control]
-    1.a Implement image inversion and build / test IP
-    1.b Implement interactive image layer extraction / exclusion using modified watershed algorithm.
+    
+    *1.a Implement image inversion and build / test IP*
+
+    *1.b Implement interactive image layer extraction / exclusion using modified watershed algorithm.*
 
 and 
 compare how CPU performs in comparision to our FPGA hardware that is exactly wired up to work on the kind of data we expect to provide as input.
@@ -33,11 +35,16 @@ Previously we have seen the image resizer takes in the whole data DMA makes the
 
 We intend to implement the following:
 1. make faster multichannel operations at a hardware level integrated with similar high level software constructs
-    1.a Highl Level Code structure to enable parallel operation and optimization
-    1.b Maintain same level of parallelism (multiple data streams and logical processing constructs) in H/W level
+    
+    *1.a Highl Level Code structure to enable parallel operation and optimization*
+    
+    *1.b Maintain same level of parallelism (multiple data streams and logical processing constructs) in H/W level*
+
 2. make the FPGA capable to process images in as wide range as our CPU supports
-    2.a CPU has large storage FPGA doesnot, we can make high level py code drive large data into DMA acceptable maximum chunks
-    2.b Increase number of data channels into and out of FPGA for faster processing (higher utilization).
+
+    *2.a CPU has large storage FPGA doesnot, we can make high level py code drive large data into DMA acceptable maximum chunks*
+
+    *2.b Increase number of data channels into and out of FPGA for faster processing (higher utilization).*
 
 This is how a typical openCV resizer works:
 <Data Transfer Image>