Commit f52f3dbe authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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Update README.md

parent e67ce926
......@@ -7,12 +7,18 @@ We want to use FPGA for implementing an algorithm in hardware to perform computa
# Background
CPUs are known for their general purpose use, the same GPUs can power all kinds of applications. EINAC the first computer in a sense had programmable cards, taking days to reprogram but used general purpose computations. CPU can run simulate any finite state machine but can't be reprogrammed as a hardware, for application specific needs like signal processing. For example we may implement an multiplier on the hardware level if we need we can depending on the kind of data we are going to process implement an hardware that can process the exact type of data much faster.
CPUs are known for their general purpose use, the same GPUs can power all kinds of applications. EINAC the first computer in a sense had programmable cards, taking days to reprogram but used general purpose computations, the limitation is code could be used to perform any tasks. CPU can run simulate any finite state machine but can't be reprogrammed as a hardware.
In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to compute
For application specific needs like signal processing wiring a device to do particular computations can prove much more efficient. We may implement an multiplier on the hardware level if we want. Depending on the kind of data we are can implement an hardware that can entirely process the exact type of data much faster. In CPU the hardware is static so all data will get converted to the same set of specific instruction set that runs one at a time in CPU.
If we know we will be doing a matrix addition for 2 4x4 array we can simply implement a register to register connected adder that will always give us the result of addition in the next cycle the data is received. In CPU we cant simply do that!
In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to compute :
1. The weight matrix of a neural network
or
2. Do a liner search
2. Array addition
or
3. Do a liner search
and
compare how CPU performs in comparision to our FPGA hardware that is exactly wired up to work on the kind of data we expect to provide as input.
......@@ -22,7 +28,9 @@ First we need to determine the type of data we would be using in our project. Ba
After this we need to determine a mental sketch of the hardware that if implemented can make the processing faster.
Next we need to know what high level functions transfer to which hardware component and write the code as per the hardware architechture we define in previous step.
#### At this point we will do a project estimate analysis and select one of the above problem statement if needed (to fit within the time)
Next we need to know what high level functions transfer to which hardware component and write the code as per the hardware architechture we define in previous step.
After this we are goingto use the HLS tool Vitis to desgin and then use Vivado to generate our harware programmable bitstream for us, this bitstream configured will be used to process our data. We will be using python APIs to interact with our bitstream.
......@@ -33,13 +41,15 @@ Then finally we can check the runtime and reach a conclusion on which is faster
# Tasks
The Tasks and maximum estimated time:
0. Problem statement and solution Plan brainstorming : 12 hrs
1. Pseudo code and solution adjustment : 3 hrs
2. Vivado study of other solutions, available tools, code and hardware correlation : 12 hrs
3. Writting the code in Vivado : 3 hrs
4. Implementing code and checking hardware features and making final adjustments : 5 hrs
5. Bitstream generation python code for overlay : 2 hrs
6. Implementing same algorithm in python CPU : 3 hrs
0. Problem statement and solution Plan brainstorming on all 3 problems : 12 hrs
1. Pseudo code and solution adjustment : 6 hrs
2. Do a project ETA analysis and goto task #2 or repeat task #0-#1 : 0 - 12 hrs
3. Vivado study of other solutions, available tools, code and hardware correlation : 12 hrs
4. Writting the code in Vivado : 3 hrs
5. Implementing code and checking hardware features and making final adjustments : 5 hrs
6. Bitstream generation python code for overlay : 2 hrs
7. Implementing same algorithm in python CPU : 3 hrs
8. Drafting the report and Analysis : 4 hrs
# Resources and Future questions
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