Commit e09e8a26 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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Update README.md

parent c8583eb9
......@@ -58,3 +58,9 @@ https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_stream_library.html
https://dspace.mit.edu/bitstream/handle/1721.1/91829/894228451-MIT.pdf?sequence=2&isAllowed=y
https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/accelerating-databases-with-fpgas.pdf
https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_process.html#djn1584047476918
# Errors and Issues encountered
[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
/color_filter/ap_start
When ap_Ctrl = None not specified in design
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