Commit d3ee8c71 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
Browse files

Update Read_for_synthesis.md

parent ef80cf14
### To synthesize the circuit from cpp file please clone the repository:
1. *run make
2. *using the zip file generated import IP to Vivado
3. *connect up as described in the Design_1.pdf
4. *generate bitstream
1. *run make*
2. *using the zip file generated import IP to Vivado*
3. *connect up as described in the Design_1.pdf*
4. *generate bitstream*
Fallback: In case make file gives error
1. *Create new project
2. *use edge_filter.cpp as design file in project
3. *synthesize
4. *export IP as zip file
5. *using zip file generated import IP to Vivado
3. *connect up as described in the Design_1.pdf
4. *generate bitstream
1. *Create new project*
2. *use edge_filter.cpp as design file in project*
3. *synthesize*
4. *export IP as zip file*
5. *using zip file generated import IP to Vivado*
3. *connect up as described in the Design_1.pdf*
4. *generate bitstream*
#### With the bit file tcl and hwh file generated by Vivado use the two notebooks to test the IP.
#### Also make sure to keep the 1.tiff , 2.tiff ... or any other single band images in same folder as IP.
#### Next use the notebooks Image_Flter_FPGA_CPU.ipynb (for checking how the IP works on single file)
#### or use Notebook_Speed_Comparison.ipynb
###### With the bit file tcl and hwh file generated by Vivado use the two notebooks to test the IP.
###### Also make sure to keep the 1.tiff , 2.tiff ... or any other single band images in same folder as IP.
###### Next keep the notebooks Image_Flter_FPGA_CPU.ipynb (for checking how the IP works on single file) and run it
###### or use Notebook_Speed_Comparison.ipynb (for speed comparison) and run it.
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