Commit cf66df38 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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Update README.md

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......@@ -6,17 +6,15 @@ fpga for streamlining of computation intensive tasks. In this case we take an hy
We want to use FPGA for implementing an algorithm in hardware to perform computation more effeciently. CPU hardware is non-flexible so the code runs using the same set of registers and ALU , we cant optimize the harware as per our code. Our objective here is to harware a processing unit (something smilar to a flexible ALU using the CLBs) in the FPGA using High level code.
## Background
<b>*FPGA should be able to process multiple streams in synchronized manner. We want to process the streams coming from an image and process them through a convolution algorithm (Robert's matrix) and then use another function to filter out relevant parts*</b>
CPUs are known for their general purpose use, the same GPUs can power all kinds of applications. CPU can run simulate any finite state machine but can't be reprogrammed as a hardware. In CPU the hardware is static so all data will get converted to the same set of specific instruction set that runs one at a time in CPU.
## Problem background
<b>*For applications like real time image processing, using CPU resource can be expensive, and the reaction time may increase in applications where decisions are based on calculations. We need a dedicated hardware that can process continous process of data coming in from sensors or camera endlessly.*</b>
In FPGA for example may implement multiple multipliers or registers to work in parallel or in specifc order on the hardware level if we want. Depending on the kind of data we would receive we can implement an hardware that can entirely process the exact type of data much faster.
<b>*FPGA should be able to process multiple streams in synchronized manner. We want to process the streams coming from an image and process them through a convolution algorithm (Robert's matrix) and then use another function to filter out relevant parts*</b>
## Objective
Our objective is to use enable continous data stream processing in a pipeline that runs faster using FPGA in comparison to CPU.
We try to implement a image-filter which works by taking data streams and processing them on fly, and the FPGA should work faster than CPU. Our objective is not to make the image-processing-algorithm fast.
We try to implement a image-filter which works by taking data streams and processing them on real time, and the FPGA should work faster than CPU. Our objective is not to make the image-processing-algorithm fast.
We should be able to:
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