Commit ca7a0270 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
Browse files

Update Instructions to run

parent e0a0c487
......@@ -12,9 +12,15 @@ Fallback: In case make file gives error
3. *synthesize*
4. *export IP as zip file*
5. *using zip file generated import IP to Vivado*
3. *connect up as described in the Design_1.pdf*
3. *connect up as described in the design_1.pdf*
4. *generate bitstream*
Fallback: In case both of above fails
1. *Use edge_filter.zip the premade ip , import it in Vivado*
2. *Make connections as shown in the design_1.pdf file*
3. *Generate bitstream*
###### With the bit file tcl and hwh file generated by Vivado use the two notebooks to test the IP.
###### Also make sure to keep the 1.tiff , 2.tiff ... or any other single band images in same folder as IP.
###### Next keep the notebooks Image_Flter_FPGA_CPU.ipynb (for checking how the IP works on single file) and run it
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment