Commit c5c528d8 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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Update README.md

parent 7a199903
......@@ -4,16 +4,16 @@ fpga for streamlining of computation intensive tasks. Like in cases where signal
### I Have tried to build a implementation from scratch where all code structure were created so we can have much higher control over design. It was sucessful and for very large images and continous streams FPGA performance shoots up as much as 3 times.
|Index| Title | Content |
|1| ------ | ------ |
|2| Overview | Why do we use FPGA |
|3| Problem background | Where can we apply our methods and get results |
|4| Objective | Our vision of the solution |
|5| Implementation | The Hardware architechture and HLS code constructs |
|6| Robert's cross | The algorithm we implemented |
|7| What we achieved and Caveats | (RESULTS) Objectives sucessful and limitations |
|8| Future Scope | Possible use in multiagent robot control using continous streaming |
|9| Tasks , Errors , References | Epilogue |
| Index | Title | Content |
| - | ------ | ------ |
| 1 | Overview | Why do we use FPGA |
| 2 | Problem background | Where can we apply our methods and get results |
| 3 | Objective | Our vision of the solution |
| 4 | Implementation | The Hardware architechture and HLS code constructs |
| 5 | Robert's cross | The algorithm we implemented |
| 6 | What we achieved and Caveats | (RESULTS) Objectives sucessful and limitations |
| 7 | Future Scope | Possible use in multiagent robot control using continous streaming |
| 8 | Tasks , Errors , References | Epilogue |
## Overview
We want to use FPGA for implementing an algorithm in hardware to perform computation more effeciently. CPU hardware is non-flexible so the code runs using the same set of registers and ALU , we cant optimize the harware as per our code. Our objective here is to harware a processing unit (something smilar to a flexible ALU using the CLBs) in the FPGA using High level code.
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