Update README.md

README.md

@@ -54,13 +54,16 @@ Hardware based Neural networks : https://users.ece.cmu.edu/~pgrover/teaching/fil
 https://www.amiq.com/consulting/2018/12/14/how-to-implement-a-convolutional-neural-network-using-high-level-synthesis/
 https://wiki.nus.edu.sg/display/ee4218/Hardware+Implementation+Flow
 
-https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_stream_library.html
-https://dspace.mit.edu/bitstream/handle/1721.1/91829/894228451-MIT.pdf?sequence=2&isAllowed=y
-https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/accelerating-databases-with-fpgas.pdf
-https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_process.html#djn1584047476918
+Operation with stream: https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_stream_library.html#ivv1539734234667__ad398476
+Specialized Constructs : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/special_graph_constructs.html?hl=template
+Database in FPGA : https://dspace.mit.edu/bitstream/handle/1721.1/91829/894228451-MIT.pdf?sequence=2&isAllowed=y
+Database in FPGA : https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/accelerating-databases-with-fpgas.pdf
+Database in FPGA  : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_process.html#djn1584047476918
 
 # Errors and Issues encountered
  [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
 Please check your design and connect them as needed: 
 /color_filter/ap_start
 When ap_Ctrl = None not specified in design
+
+Cant find custom IP in Vivado : add IP zip path, open IP Integrator view, from IP configure window manually add the IP