Commit b0d378fb authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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parent e09e8a26
......@@ -54,13 +54,16 @@ Hardware based Neural networks :
Operation with stream:
Specialized Constructs :
Database in FPGA :
Database in FPGA :
Database in FPGA :
# Errors and Issues encountered
[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed:
When ap_Ctrl = None not specified in design
Cant find custom IP in Vivado : add IP zip path, open IP Integrator view, from IP configure window manually add the IP
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