Commit 95f68710 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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Update README.md

parent 3fe57f45
......@@ -14,11 +14,11 @@ For application specific needs like signal processing wiring a device to do part
If we know we will be doing a matrix addition for 2 4x4 array we can simply implement a register to register connected adder that will always give us the result of addition in the next cycle the data is received. In CPU we cant simply do that!
In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to compute :
1. The weight matrix of a neural network [Future Application to develop a hardware optimized neural network in final thesis]
1. *The weight matrix of a neural network* [Future Application to develop a hardware optimized neural network in final thesis]
or
2. Array addition [Future application to explore accelaration in a FIR filter]
2. *2D matrix operation* [Future application to explore accelaration in a FIR filter]
or
3. Do a linear search [Future application to implement a hardware optimized for a fast database]
3. *Do a linear search* [Future application to implement a hardware optimized for a fast database]
and
compare how CPU performs in comparision to our FPGA hardware that is exactly wired up to work on the kind of data we expect to provide as input.
......
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