Commit 8f582f5a authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
Browse files

Adding instruction to run

parent 77410cc4
### To synthesize the circuit from cpp file please clone the repository:
1. _run make
2. _using the zip file generated import IP to Vivado
3. _connect up as described in the Design_1.pdf
4. _generate bitstream
Fallback: In case make file gives error
1. _Create new project
2. _use edge_filter.cpp as design file in project
3. _synthesize
4. _export IP as zip file
5. _using zip file generated import IP to Vivado
3. _connect up as described in the Design_1.pdf
4. _generate bitstream
#### With the bit file tcl and hwh file generated by Vivado use the two notebooks to test the IP.
#### Also make sure to keep the 1.tiff , 2.tiff ... or any other single band images in same folder as IP.
#### Next use the notebooks Image_Flter_FPGA_CPU.ipynb (for checking how the IP works on single file)
#### or use Notebook_Speed_Comparison.ipynb
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