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Sabyasachi Mondal
FPGA_final_project
Commits
7f4faa33
Commit
7f4faa33
authored
May 22, 2021
by
Sabyasachi Mondal
Browse files
Update col_filter.tcl
parent
8d158205
Changes
1
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col_filter.tcl
View file @
7f4faa33
...
...
@@ -169,11 +169,27 @@ proc create_root_design { parentCell } {
CONFIG.c_sg_include_stscntrl_strm
{
0
}
\
]
$axi_dma_0
# Create instance: axi_dma_1, and set properties
set axi_dma_1
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_1
]
set_property -dict
[
list
\
CONFIG.c_include_s2mm
{
1
}
\
CONFIG.c_include_sg
{
0
}
\
CONFIG.c_sg_include_stscntrl_strm
{
0
}
\
]
$axi_dma_1
# Create instance: axi_dma_2, and set properties
set axi_dma_2
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_2
]
set_property -dict
[
list
\
CONFIG.c_include_s2mm
{
0
}
\
CONFIG.c_include_sg
{
0
}
\
CONFIG.c_sg_include_stscntrl_strm
{
0
}
\
]
$axi_dma_2
# Create instance: axi_mem_intercon, and set properties
set axi_mem_intercon
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon
]
set_property -dict
[
list
\
CONFIG.NUM_MI
{
1
}
\
CONFIG.NUM_SI
{
2
}
\
CONFIG.NUM_SI
{
5
}
\
]
$axi_mem_intercon
# Create instance: color_filter_0, and set properties
...
...
@@ -192,33 +208,46 @@ proc create_root_design { parentCell } {
# Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph
]
set_property -dict
[
list
\
CONFIG.NUM_MI
{
2
}
\
CONFIG.NUM_MI
{
4
}
\
]
$ps7_0_axi_periph
# Create instance: rst_ps7_0_50M, and set properties
set rst_ps7_0_50M
[
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_50M
]
# Create interface connections
connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S
[
get_bd_intf_pins axi_dma_0/M_AXIS_MM2S
]
[
get_bd_intf_pins color_filter_0/din
]
connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S
[
get_bd_intf_pins axi_dma_0/M_AXIS_MM2S
]
[
get_bd_intf_pins color_filter_0/din
_r
]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S
[
get_bd_intf_pins axi_dma_0/M_AXI_MM2S
]
[
get_bd_intf_pins axi_mem_intercon/S00_AXI
]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM
[
get_bd_intf_pins axi_dma_0/M_AXI_S2MM
]
[
get_bd_intf_pins axi_mem_intercon/S01_AXI
]
connect_bd_intf_net -intf_net axi_dma_1_M_AXIS_MM2S
[
get_bd_intf_pins axi_dma_1/M_AXIS_MM2S
]
[
get_bd_intf_pins color_filter_0/din_y
]
connect_bd_intf_net -intf_net axi_dma_1_M_AXI_MM2S
[
get_bd_intf_pins axi_dma_1/M_AXI_MM2S
]
[
get_bd_intf_pins axi_mem_intercon/S02_AXI
]
connect_bd_intf_net -intf_net axi_dma_1_M_AXI_S2MM
[
get_bd_intf_pins axi_dma_1/M_AXI_S2MM
]
[
get_bd_intf_pins axi_mem_intercon/S03_AXI
]
connect_bd_intf_net -intf_net axi_dma_2_M_AXIS_MM2S
[
get_bd_intf_pins axi_dma_2/M_AXIS_MM2S
]
[
get_bd_intf_pins color_filter_0/din_b
]
connect_bd_intf_net -intf_net axi_dma_2_M_AXI_MM2S
[
get_bd_intf_pins axi_dma_2/M_AXI_MM2S
]
[
get_bd_intf_pins axi_mem_intercon/S04_AXI
]
connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI
[
get_bd_intf_pins axi_mem_intercon/M00_AXI
]
[
get_bd_intf_pins processing_system7_0/S_AXI_HP0
]
connect_bd_intf_net -intf_net color_filter_0_dout
[
get_bd_intf_pins axi_dma_0/S_AXIS_S2MM
]
[
get_bd_intf_pins color_filter_0/dout
]
connect_bd_intf_net -intf_net color_filter_0_dout_inv
[
get_bd_intf_pins axi_dma_0/S_AXIS_S2MM
]
[
get_bd_intf_pins color_filter_0/dout_inv
]
connect_bd_intf_net -intf_net color_filter_0_dout_seg
[
get_bd_intf_pins axi_dma_1/S_AXIS_S2MM
]
[
get_bd_intf_pins color_filter_0/dout_seg
]
connect_bd_intf_net -intf_net processing_system7_0_DDR
[
get_bd_intf_ports DDR
]
[
get_bd_intf_pins processing_system7_0/DDR
]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO
[
get_bd_intf_ports FIXED_IO
]
[
get_bd_intf_pins processing_system7_0/FIXED_IO
]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0
[
get_bd_intf_pins processing_system7_0/M_AXI_GP0
]
[
get_bd_intf_pins ps7_0_axi_periph/S00_AXI
]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI
[
get_bd_intf_pins color_filter_0/s_axi_control
]
[
get_bd_intf_pins ps7_0_axi_periph/M00_AXI
]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI
[
get_bd_intf_pins axi_dma_0/S_AXI_LITE
]
[
get_bd_intf_pins ps7_0_axi_periph/M01_AXI
]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI
[
get_bd_intf_pins axi_dma_0/S_AXI_LITE
]
[
get_bd_intf_pins ps7_0_axi_periph/M00_AXI
]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI
[
get_bd_intf_pins axi_dma_1/S_AXI_LITE
]
[
get_bd_intf_pins ps7_0_axi_periph/M01_AXI
]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI
[
get_bd_intf_pins axi_dma_2/S_AXI_LITE
]
[
get_bd_intf_pins ps7_0_axi_periph/M02_AXI
]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI
[
get_bd_intf_pins color_filter_0/s_axi_control
]
[
get_bd_intf_pins ps7_0_axi_periph/M03_AXI
]
# Create port connections
connect_bd_net -net processing_system7_0_FCLK_CLK0
[
get_bd_pins axi_dma_0/m_axi_mm2s_aclk
]
[
get_bd_pins axi_dma_0/m_axi_s2mm_aclk
]
[
get_bd_pins axi_dma_0/s_axi_lite_aclk
]
[
get_bd_pins axi_mem_intercon/ACLK
]
[
get_bd_pins axi_mem_intercon/M00_ACLK
]
[
get_bd_pins axi_mem_intercon/S00_ACLK
]
[
get_bd_pins axi_mem_intercon/S01_ACLK
]
[
get_bd_pins color_filter_0/ap_clk
]
[
get_bd_pins processing_system7_0/FCLK_CLK0
]
[
get_bd_pins processing_system7_0/M_AXI_GP0_ACLK
]
[
get_bd_pins processing_system7_0/S_AXI_HP0_ACLK
]
[
get_bd_pins ps7_0_axi_periph/ACLK
]
[
get_bd_pins ps7_0_axi_periph/M00_ACLK
]
[
get_bd_pins ps7_0_axi_periph/M01_ACLK
]
[
get_bd_pins ps7_0_axi_periph/S00_ACLK
]
[
get_bd_pins rst_ps7_0_50M/slowest_sync_clk
]
connect_bd_net -net processing_system7_0_FCLK_CLK0
[
get_bd_pins axi_dma_0/m_axi_mm2s_aclk
]
[
get_bd_pins axi_dma_0/m_axi_s2mm_aclk
]
[
get_bd_pins axi_dma_0/s_axi_lite_aclk
]
[
get_bd_pins
axi_dma_1/m_axi_mm2s_aclk
]
[
get_bd_pins axi_dma_1/m_axi_s2mm_aclk
]
[
get_bd_pins axi_dma_1/s_axi_lite_aclk
]
[
get_bd_pins axi_dma_2/m_axi_mm2s_aclk
]
[
get_bd_pins axi_dma_2/s_axi_lite_aclk
]
[
get_bd_pins
axi_mem_intercon/ACLK
]
[
get_bd_pins axi_mem_intercon/M00_ACLK
]
[
get_bd_pins axi_mem_intercon/S00_ACLK
]
[
get_bd_pins axi_mem_intercon/S01_ACLK
]
[
get_bd_pins
axi_mem_intercon/S02_ACLK
]
[
get_bd_pins axi_mem_intercon/S03_ACLK
]
[
get_bd_pins axi_mem_intercon/S04_ACLK
]
[
get_bd_pins
color_filter_0/ap_clk
]
[
get_bd_pins processing_system7_0/FCLK_CLK0
]
[
get_bd_pins processing_system7_0/M_AXI_GP0_ACLK
]
[
get_bd_pins processing_system7_0/S_AXI_HP0_ACLK
]
[
get_bd_pins ps7_0_axi_periph/ACLK
]
[
get_bd_pins ps7_0_axi_periph/M00_ACLK
]
[
get_bd_pins ps7_0_axi_periph/M01_ACLK
]
[
get_bd_pins
ps7_0_axi_periph/M02_ACLK
]
[
get_bd_pins ps7_0_axi_periph/M03_ACLK
]
[
get_bd_pins
ps7_0_axi_periph/S00_ACLK
]
[
get_bd_pins rst_ps7_0_50M/slowest_sync_clk
]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N
[
get_bd_pins processing_system7_0/FCLK_RESET0_N
]
[
get_bd_pins rst_ps7_0_50M/ext_reset_in
]
connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn
[
get_bd_pins axi_dma_0/axi_resetn
]
[
get_bd_pins axi_mem_intercon/ARESETN
]
[
get_bd_pins axi_mem_intercon/M00_ARESETN
]
[
get_bd_pins axi_mem_intercon/S00_ARESETN
]
[
get_bd_pins axi_mem_intercon/S01_ARESETN
]
[
get_bd_pins color_filter_0/ap_rst_n
]
[
get_bd_pins ps7_0_axi_periph/ARESETN
]
[
get_bd_pins ps7_0_axi_periph/M00_ARESETN
]
[
get_bd_pins ps7_0_axi_periph/M01_ARESETN
]
[
get_bd_pins ps7_0_axi_periph/S00_ARESETN
]
[
get_bd_pins rst_ps7_0_50M/peripheral_aresetn
]
connect_bd_net -net rst_ps7_0_50M_peripheral_aresetn
[
get_bd_pins axi_dma_0/axi_resetn
]
[
get_bd_pins
axi_dma_1/axi_resetn
]
[
get_bd_pins axi_dma_2/axi_resetn
]
[
get_bd_pins
axi_mem_intercon/ARESETN
]
[
get_bd_pins axi_mem_intercon/M00_ARESETN
]
[
get_bd_pins axi_mem_intercon/S00_ARESETN
]
[
get_bd_pins axi_mem_intercon/S01_ARESETN
]
[
get_bd_pins
axi_mem_intercon/S02_ARESETN
]
[
get_bd_pins axi_mem_intercon/S03_ARESETN
]
[
get_bd_pins axi_mem_intercon/S04_ARESETN
]
[
get_bd_pins
color_filter_0/ap_rst_n
]
[
get_bd_pins ps7_0_axi_periph/ARESETN
]
[
get_bd_pins ps7_0_axi_periph/M00_ARESETN
]
[
get_bd_pins ps7_0_axi_periph/M01_ARESETN
]
[
get_bd_pins
ps7_0_axi_periph/M02_ARESETN
]
[
get_bd_pins ps7_0_axi_periph/M03_ARESETN
]
[
get_bd_pins
ps7_0_axi_periph/S00_ARESETN
]
[
get_bd_pins rst_ps7_0_50M/peripheral_aresetn
]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space
[
get_bd_addr_spaces axi_dma_0/Data_MM2S
]
[
get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM
]
-force
assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space
[
get_bd_addr_spaces axi_dma_0/Data_S2MM
]
[
get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM
]
-force
assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space
[
get_bd_addr_spaces axi_dma_1/Data_MM2S
]
[
get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM
]
-force
assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space
[
get_bd_addr_spaces axi_dma_1/Data_S2MM
]
[
get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM
]
-force
assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space
[
get_bd_addr_spaces axi_dma_2/Data_MM2S
]
[
get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM
]
-force
assign_bd_address -offset 0x41E00000 -range 0x00010000 -target_address_space
[
get_bd_addr_spaces processing_system7_0/Data
]
[
get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg
]
-force
assign_bd_address -offset 0x41E10000 -range 0x00010000 -target_address_space
[
get_bd_addr_spaces processing_system7_0/Data
]
[
get_bd_addr_segs axi_dma_1/S_AXI_LITE/Reg
]
-force
assign_bd_address -offset 0x41E20000 -range 0x00010000 -target_address_space
[
get_bd_addr_spaces processing_system7_0/Data
]
[
get_bd_addr_segs axi_dma_2/S_AXI_LITE/Reg
]
-force
assign_bd_address -offset 0x40000000 -range 0x00010000 -target_address_space
[
get_bd_addr_spaces processing_system7_0/Data
]
[
get_bd_addr_segs color_filter_0/s_axi_control/Reg
]
-force
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