Commit 6b3de598 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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Update README.md

parent 2db15b7d
......@@ -55,6 +55,7 @@ Database in FPGA : https://dspace.mit.edu/bitstream/handle/1721.1/91829/89422845
Database in FPGA : https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/accelerating-databases-with-fpgas.pdf
Database in FPGA : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_process.html#djn1584047476918
Vitis Examples : https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/cpp_kernels/README.md
Running Accelerator : https://pynq.readthedocs.io/en/v2.6.1/pynq_alveo.html#running-accelerators
##### Future topics
A great resource for 32x32 image dataset: http://chaladze.com/l5/
Book to jumstart or serve as refresher: Programming Machine Learning (Perrotta, Paolo) [ISBN: , 9781680507720]
......@@ -72,4 +73,3 @@ Cant find custom IP in Vivado : add IP zip path, open IP Integrator view, from I
Cant connect hls::stream<> type object in IP : Note: The hls::stream class should always be passed between functions as a C++ reference argument. For example, &my_stream.
IMPORTANT: The hls::stream class is only used in C++ designs. Array of streams is not supported.
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