Update README.md

README.md

@@ -56,6 +56,7 @@ Database in FPGA : https://www.xilinx.com/publications/events/developer-forum/20
 Database in FPGA  : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_process.html#djn1584047476918
 Vitis Examples : https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/cpp_kernels/README.md
 Running Accelerator : https://pynq.readthedocs.io/en/v2.6.1/pynq_alveo.html#running-accelerators
+Pragma Interfaces : https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/jit1504034365862.html
 ##### Future topics
 A great resource for 32x32 image dataset: http://chaladze.com/l5/
 Book to jumstart or serve as refresher: Programming Machine Learning (Perrotta, Paolo) [ISBN: , 9781680507720]
@@ -73,3 +74,5 @@ Cant find custom IP in Vivado : add IP zip path, open IP Integrator view, from I
 
 Cant connect hls::stream<> type object in IP : Note: The hls::stream class should always be passed between functions as a C++ reference argument. For example, &my_stream.
 IMPORTANT: The hls::stream class is only used in C++ designs. Array of streams is not supported.
+
+Non-Blocking write not-allowed in Non-FIFO Interfaces like axis instead try using FIFO m_axi