Commit 63376ed2 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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parent 6b3de598
......@@ -56,6 +56,7 @@ Database in FPGA :
Database in FPGA :
Vitis Examples :
Running Accelerator :
Pragma Interfaces :
##### Future topics
A great resource for 32x32 image dataset:
Book to jumstart or serve as refresher: Programming Machine Learning (Perrotta, Paolo) [ISBN: , 9781680507720]
......@@ -73,3 +74,5 @@ Cant find custom IP in Vivado : add IP zip path, open IP Integrator view, from I
Cant connect hls::stream<> type object in IP : Note: The hls::stream class should always be passed between functions as a C++ reference argument. For example, &my_stream.
IMPORTANT: The hls::stream class is only used in C++ designs. Array of streams is not supported.
Non-Blocking write not-allowed in Non-FIFO Interfaces like axis instead try using FIFO m_axi
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