Commit 53bc287a authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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Update README.md

parent 863f1f60
......@@ -14,7 +14,7 @@ For application specific needs like signal processing wiring a device to do part
If we know we will be doing a matrix addition for 2 4x4 array we can simply implement a register to register connected adder that will always give us the result of addition in the next cycle the data is received. In CPU we cant simply do that!
In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to compute :
1. *The weight matrix of a neural network* [Future Application to develop a hardware optimized neural network in final thesis]
1. *The weight matrix of a neural network* [Future Application to develop a hardware optimized neural network]
or
2. *Finfing the nonce in Ethereum* [Future Application to find out if encoding is faster in FPGA]
or
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