Commit 524d86ad authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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Update README.md

parent 88cddfea
......@@ -19,9 +19,11 @@ But We can break the same stereotype and as software designers develop our own a
Our Objective is to develop better integrated code such that our hardware and software works hand in hand to deliver the best result. We start thinking of a algorithm in python and think how it can be optimized while running it in the FPGA's Logic Unit. We would develop the hardware in C++ and write/burn the hardware in FPGA and use our Py code to drive it.
In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to perform image processing (like inversion, color swap, color sieve) at a much faster rate:
In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to perform image processing (like inversion, color specific background sieve) at a much faster rate:
1. *Perform Image processing by using the registers, streaming Interface and DMA* [Future scope multi-agent control]
1. *Perform Image processing by using the registers, axi_streaming and DMA* [Future scope multi-agent control]
1.a Implement image inversion and build / test IP
1.b Implement interactive image layer extraction / exclusion using modified watershed algorithm.
and
compare how CPU performs in comparision to our FPGA hardware that is exactly wired up to work on the kind of data we expect to provide as input.
......@@ -31,7 +33,11 @@ Previously we have seen the image resizer takes in the whole data DMA makes the
We intend to implement the following:
1. make faster multichannel operations at a hardware level integrated with similar high level software constructs
1.a Highl Level Code structure to enable parallel operation and optimization
1.b Maintain same level of parallelism (multiple data streams and logical processing constructs) in H/W level
2. make the FPGA capable to process images in as wide range as our CPU supports
2.a CPU has large storage FPGA doesnot, we can make high level py code drive large data into DMA acceptable maximum chunks
2.b Increase number of data channels into and out of FPGA for faster processing (higher utilization).
This is how a typical openCV resizer works:
<Data Transfer Image>
......@@ -45,16 +51,8 @@ This may be made more efficient and robust (accomodating any image width) if by
We use two streams of data in each process with it's own processing unit in our IP , which can be schematically represented in:
<image for our Implementation>
###### At this point we will do a project estimate analysis and select one of the above problem statement if needed (to fit within the time)
Next we need to know what high level functions transfer to which hardware component and write the code as per the hardware architechture we define in previous step.
After this we are goingto use the HLS tool Vitis to desgin and then use Vivado to generate our harware programmable bitstream for us, this bitstream configured will be used to process our data. We will be using python APIs to interact with our bitstream.
Next we implement the same algorithm in our python code that will obviously run on the cpu.
Then finally we can check the runtime and reach a conclusion on which is faster and why.
In the background extraction technique we use a modified form of the watershed algorithm to suit different layers of the image with a similar range and intensity of pixels, so we have a customizable tayer to extract.
<Image modified watershed>
# Tasks
The Tasks and maximum estimated time:
......@@ -62,12 +60,13 @@ The Tasks and maximum estimated time:
1. Problem statement and brainstorming for project selection : *24 hrs*
2. Design a basic model and build overlay : *4 hrs*
3. Python code adjustment and integration : *3 hrs*
4. Implement next stage of overlay design : *_ hrs*
4. Plan next stage of overlay design : *2 hrs*
# Resources used and Future project topics
#### Resources used
Image segmentation : https://theailearner.com/2020/11/29/image-segmentation-with-watershed-algorithm/
Operation with stream: https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_stream_library.html#ivv1539734234667__ad398476
Specialized Constructs : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/special_graph_constructs.html?hl=template
Database in FPGA : https://dspace.mit.edu/bitstream/handle/1721.1/91829/894228451-MIT.pdf?sequence=2&isAllowed=y
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