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Sabyasachi Mondal
FPGA_final_project
Commits
424d9dc4
Commit
424d9dc4
authored
May 30, 2021
by
Harald Keller
Browse files
Commit author name
parent
25cfab7b
Changes
2
Hide whitespace changes
Inline
Side-by-side
.ipynb_checkpoints/Filter_fpga_Driven-checkpoint.ipynb
View file @
424d9dc4
%% Cell type:markdown id: tags:
## Greenfield implementation of Edge Filter
Streaming in pixel data in 3xRow format to be fed to filter kernel and produce an edgemap
%% Cell type:code id: tags:
```
python
from
PIL
import
Image
as
img
from
pynq
import
Overlay
,
allocate
,
Xlnk
import
pynq.lib.dma
import
numpy
as
np
import
matplotlib.pyplot
as
plt
```
%%%% Output: display_data
%%%% Output: display_data
%% Cell type:code id: tags:
```
python
arr_2d
=
np
.
array
(
img
.
open
(
'lakemead_2004.jpg'
))
(
h
,
w
)
=
arr_2d
.
shape
arr
=
np
.
reshape
(
arr_2d
,(
h
*
w
))
print
(
arr_2d
.
shape
)
print
(
arr
.
shape
)
plt
.
imshow
(
arr_2d
)
```
%%%% Output: stream
(405, 540)
(218700,)
%%%% Output: execute_result
<matplotlib.image.AxesImage at 0xac7e5f70>
%%%% Output: display_data
%% Cell type:code id: tags:
```
python
oly
=
Overlay
(
'design_1.bit'
)
oly
.
download
()
```
%% Cell type:code id: tags:
```
python
LEN
=
w
oly
.
edge_filter_0
.
write
(
0x10
,
LEN
)
dma0
=
oly
.
axi_dma_0
dma1
=
oly
.
axi_dma_1
dma2
=
oly
.
axi_dma_2
dma3
=
oly
.
axi_dma_3
```
%% Cell type:code id: tags:
```
python
out_arr
=
[]
for
i
in
arr_2d
[
0
:(
len
(
arr_2d
)
-
2
)]:
in_ch0
=
allocate
(
shape
=
(
LEN
,),
dtype
=
np
.
int32
)
in_ch1
=
allocate
(
shape
=
(
LEN
,),
dtype
=
np
.
int32
)
in_ch2
=
allocate
(
shape
=
(
LEN
,),
dtype
=
np
.
int32
)
op_ch0
=
allocate
(
shape
=
(
LEN
,),
dtype
=
np
.
int32
)
in_ch0
[:]
=
arr
[
i
]
in_ch1
[:]
=
arr
[
i
+
1
]
in_ch2
[:]
=
arr
[
i
+
2
]
dma0
.
sendchannel
.
transfer
(
in_ch0
)
dma1
.
sendchannel
.
transfer
(
in_ch1
)
dma2
.
sendchannel
.
transfer
(
in_ch2
)
oly
.
edge_filter_0
.
write
(
0x0
,
0x1
)
dma3
.
recvchannel
.
start
()
dma3
.
recvchannel
.
transfer
(
op_ch0
)
dma0
.
sendchannel
.
wait
()
dma1
.
sendchannel
.
wait
()
dma2
.
sendchannel
.
wait
()
out_arr
.
append
(
op_ch0
)
del
in_ch0
del
in_ch1
del
in_ch2
del
op_ch0
```
%% Cell type:code id: tags:
```
python
img_sobel
=
(
np
.
array
(
out_arr
)).
reshape
(
h
-
2
,
w
)
```
%% Cell type:code id: tags:
```
python
plt
.
imshow
(
img_sobel
.
astype
(
'uint8'
))
```
%%%% Output: execute_result
<matplotlib.image.AxesImage at 0xaca4ea10>
%%%% Output: display_data
%% Cell type:markdown id: tags:
#### I now have an answer to why the DMAs were not working , we just need to remember to check the status 0x0,0x30 or shifter by 0x4 for readers.
#### The DMA controls and synchrniztion in Hostcode and Kernelcode should be properly handled
%% Cell type:markdown id: tags:
#### Now the filter logic seems to be weird Need to Fix that !!
%% Cell type:code id: tags:
```
python
```
...
...
Filter_fpga_Driven.ipynb
View file @
424d9dc4
%% Cell type:markdown id: tags:
## Greenfield implementation of Edge Filter
Streaming in pixel data in 3xRow format to be fed to filter kernel and produce an edgemap
%% Cell type:code id: tags:
```
python
from
PIL
import
Image
as
img
from
pynq
import
Overlay
,
allocate
,
Xlnk
import
pynq.lib.dma
import
numpy
as
np
import
matplotlib.pyplot
as
plt
```
%%%% Output: display_data
%%%% Output: display_data
%% Cell type:code id: tags:
```
python
arr_2d
=
np
.
array
(
img
.
open
(
'lakemead_2004.jpg'
))
(
h
,
w
)
=
arr_2d
.
shape
arr
=
np
.
reshape
(
arr_2d
,(
h
*
w
))
print
(
arr_2d
.
shape
)
print
(
arr
.
shape
)
plt
.
imshow
(
arr_2d
)
```
%%%% Output: stream
(405, 540)
(218700,)
%%%% Output: execute_result
<matplotlib.image.AxesImage at 0xac7e5f70>
%%%% Output: display_data
%% Cell type:code id: tags:
```
python
oly
=
Overlay
(
'design_1.bit'
)
oly
.
download
()
```
%% Cell type:code id: tags:
```
python
LEN
=
w
oly
.
edge_filter_0
.
write
(
0x10
,
LEN
)
dma0
=
oly
.
axi_dma_0
dma1
=
oly
.
axi_dma_1
dma2
=
oly
.
axi_dma_2
dma3
=
oly
.
axi_dma_3
```
%% Cell type:code id: tags:
```
python
out_arr
=
[]
for
i
in
arr_2d
[
0
:(
len
(
arr_2d
)
-
2
)]:
in_ch0
=
allocate
(
shape
=
(
LEN
,),
dtype
=
np
.
int32
)
in_ch1
=
allocate
(
shape
=
(
LEN
,),
dtype
=
np
.
int32
)
in_ch2
=
allocate
(
shape
=
(
LEN
,),
dtype
=
np
.
int32
)
op_ch0
=
allocate
(
shape
=
(
LEN
,),
dtype
=
np
.
int32
)
in_ch0
[:]
=
arr
[
i
]
in_ch1
[:]
=
arr
[
i
+
1
]
in_ch2
[:]
=
arr
[
i
+
2
]
dma0
.
sendchannel
.
transfer
(
in_ch0
)
dma1
.
sendchannel
.
transfer
(
in_ch1
)
dma2
.
sendchannel
.
transfer
(
in_ch2
)
oly
.
edge_filter_0
.
write
(
0x0
,
0x1
)
dma3
.
recvchannel
.
start
()
dma3
.
recvchannel
.
transfer
(
op_ch0
)
dma0
.
sendchannel
.
wait
()
dma1
.
sendchannel
.
wait
()
dma2
.
sendchannel
.
wait
()
out_arr
.
append
(
op_ch0
)
del
in_ch0
del
in_ch1
del
in_ch2
del
op_ch0
```
%% Cell type:code id: tags:
```
python
img_sobel
=
(
np
.
array
(
out_arr
)).
reshape
(
h
-
2
,
w
)
```
%% Cell type:code id: tags:
```
python
plt
.
imshow
(
img_sobel
.
astype
(
'uint8'
))
```
%%%% Output: execute_result
<matplotlib.image.AxesImage at 0xaca4ea10>
%%%% Output: display_data
%% Cell type:markdown id: tags:
#### I now have an answer to why the DMAs were not working , we just need to remember to check the status 0x0,0x30 or shifter by 0x4 for readers.
#### The DMA controls and synchrniztion in Hostcode and Kernelcode should be properly handled
%% Cell type:markdown id: tags:
#### Now the filter logic seems to be weird Need to Fix that !!
%% Cell type:code id: tags:
```
python
```
...
...
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