Commit 08b94d73 authored by Sabyasachi Mondal's avatar Sabyasachi Mondal
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# FPGA_final_project
# FPGA in Image Feature detection and comparison with CPU
#### Group4: Sabyasachi Mondal , Ravi Yadav
fpga for streamlining of computation intensive tasks. In this case we take an hyperspectral image which is generally analysed by satellites or drones mostly consisting of single band image data. This can be used for both maritime and vehicular navigation.
#### I Have tried to build a implementation from scratch where all code structure were created so we can have much higher control over design
| Title | Content |
| ------ | ------ |
| Overview | Why do we use FPGA |
| Problem background | Where can we apply our methods and get results |
| Objective | Our vision of the solution |
| Implementation | The Hardware architechture and HLS code constructs |
| Robert's cross | The algorithm we implemented |
| What we achieved and Caveats | Objectives sucessful and limitations |
| Future Scope | Possible use in multiagent robot control using continous streaming |
## Overview
We want to use FPGA for implementing an algorithm in hardware to perform computation more effeciently. CPU hardware is non-flexible so the code runs using the same set of registers and ALU , we cant optimize the harware as per our code. Our objective here is to harware a processing unit (something smilar to a flexible ALU using the CLBs) in the FPGA using High level code.
......@@ -18,9 +29,9 @@ We try to implement a image-filter which works by taking data streams and proces
We should be able to:
1. <b>*Remove limitations on length and size of data so the structure can be adapted for real-time continous use*</b>
1. <b>*Remove limitations on length and size of data so the design can be adapted for real-time continous use with streaming data*</b>
2. <b>*Enable multiple data stream processing is parallel using the ctrategies used in FPGA for faster processing*</b>
2. <b>*Enable multiple data stream processing is parallel using the strategies used in HLS for faster processing*</b>
3. <b>*FPGA should be reasonably faster than our CPU for processing streams*</b>
......@@ -30,7 +41,7 @@ Previously we have seen the image resizer takes in the whole data DMA makes the
We intend to implement the following:
1. <b>*fast multichannel stream operations at a hardware level integrated with similar high level software constructs in python*</b>
*1.a High Level Code structure to enable parallel operation and optimization in functions*
*1.a High Level Code structure in pythonto enable parallel operation and feed data continously using DMA*
*1.b Maintain same level of parallelism (multiple processing streams) in unrolled loops*
......@@ -40,7 +51,7 @@ We intend to implement the following:
*2.b Synchronized operation between packets of each stream which is essential for processing multiple togather.*
We try to read each row in the image as a pack of 3 streams process it in 2 seperate block and return the output as an array.
We try to read each row in the image as a pack of 3 streams process it in 2 seperate block and return the output as an array. *Since Robert's cross works on a specific 2x2 set of pixels of the image we must synchronize the stream of data coming in from our DMA such that if we read Nth packet in DMA A we must read Nth packet in DMA B and Nth packet in DMA C.*
![Schematic streaming rows and output](https://mygit.th-deg.de/sm11312/fpga_final_project/-/raw/main/HLSolution.JPG "Schematic streaming rows and output")
......@@ -58,16 +69,12 @@ We use two blocks to process the streams but that doesnot mean we use one thread
![Unravelling of streams in loop and parallel processing](https://mygit.th-deg.de/sm11312/fpga_final_project/-/raw/main/Parallel_process.JPG "Unravelling of streams in loop and parallel processing")
## Instructions to run
Simply clone the repository in a Pynq Z2 board and run the file "Hyperspectral_Image_Filter_FPGA_CPU_comparison.ipynb" line by line.
We should ensure the design.bit , design.hwh and design.tcl are present in the same folder as the above Jupyternotebook.
There is also a sample image lakemead_2004.jpg we may use as input to check the output of our IP.
## Instroduction to the algorithm
<br>*The RObert's operator is very effective in detecting features in an image, specifically for images with more precise features*</br>
We can also use the edge_filter.cpp file for creating an IP and generating a bitstream by designing the block diagram as shown in BlockDiagram.JPG
<br>*The Robert's operator is a 2x2 Matrix that can be used to find out differences in image bouundaries becuase of it's weights*<br>
The code should generate a output file that highlights the rough edges of the image for example contours / hills.
![Introduction to Robert's cross operation](https://homepages.inf.ed.ac.uk/rbf/HIPR2/roberts.htm "Brief introduction to Robert's cross operation")
## What we achieved and the caveat :
<b>*We intended to build a architechture that can process multiple streams and process them in same parallel level and we were sucessful.*</b>
......@@ -138,4 +145,4 @@ DMA size must be lesser than 16383 so we cant feed very large datasets directly
WARNING: [HLS 200-786] Detected dataflow-on-top in function 'color_filter' (../project_3/color_filter.cpp:45) with default interface mode 'ap_ctrl_hs'. Overlapped execution of successive kernel calls will not happen unless interface mode 'ap_ctrl_chain' is used (or 'ap_ctrl_none' for a purely data-driven design).
Resolution: For help on HLS 200-786 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-786.html
DMA Stuck and not reponding, [fixed thanks to Lauri's Blog](https://lauri.võsandi.com/hdl/zynq/xilinx-dma.html) and [problems other's face](https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Why-AXI-DMA-starts-acquiring-data-during-configuration/td-p/766605) and more [problems](https://forums.xilinx.com/t5/AXI-Infrastructure-Archive/tkeep-signal-in-AXI-DMA-and-tstrb-3-0-in-Custom-AXI-Stream-IP/td-p/921850)
DMA Stuck and not reponding, [fixed thanks to Lauri's Blog](https://lauri.võsandi.com/hdl/zynq/xilinx-dma.html) and [problems other's faced](https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Why-AXI-DMA-starts-acquiring-data-during-configuration/td-p/766605) and more [problems](https://forums.xilinx.com/t5/AXI-Infrastructure-Archive/tkeep-signal-in-AXI-DMA-and-tstrb-3-0-in-Custom-AXI-Stream-IP/td-p/921850)
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