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# FPGA_final_project
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#### Group4: Sabyasachi Mondal , Ravi Yadav
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fpga vs cpu performance comparison and fpga streamlining for computation intensive tasks
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# Overview
We want to use FPGA for implementing an algorithm in hardware to perform computation more effeciently. CPU hardware is non-flexible so the code runs using the same set of registers and ALU , we cant optimize the harware as per our code. Our objective here is to harware a processing unit (something smilar to a flexible ALU using the CLBs) in the FPGA using High level code.


# Background
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CPUs are known for their general purpose use, the same GPUs can power all kinds of applications. CPU can run simulate any finite state machine but can't be reprogrammed as a hardware. In CPU the hardware is static so all data will get converted to the same set of specific instruction set that runs one at a time in CPU.
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In FPGA for example may implement multiple multipliers or registers to work in parallel or in specifc order on the hardware level if we want. Depending on the kind of data we would receive we can implement an hardware that can entirely process the exact type of data much faster.
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For application specific needs like signal processing the CPU takes help of the same compilation techniques and the same Machine level instructions which cant be optimized except for designing better software at the high level / mid level.
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But We can break the same stereotype and as software designers develop our own algorithms bottom up from register levels to a high level code (python for example), which may prove immensely powerful for the task specific algorithm.

# Objective

Our Objective is to develop better integrated code such that our hardware and software works hand in hand to deliver the best result. We start thinking of a algorithm in python and think how it can be optimized while running it in the FPGA's Logic Unit. We would develop the hardware in C++ and write/burn the hardware in FPGA and use our Py code to drive it.  

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In this case we are going to use the FPGA to implement a processing unit in hardware from High Level C code that will be able to perform image processing (like inversion, color specific background sieve) at a much faster rate:
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1. *Perform Image processing by using the registers, axi_streaming and DMA* [Future scope multi-agent control]
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    *1.a Implement image inversion and build / test IP*

    *1.b Implement interactive image layer extraction / exclusion using modified watershed algorithm.*
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and 
compare how CPU performs in comparision to our FPGA hardware that is exactly wired up to work on the kind of data we expect to provide as input.

# Implementation Strategy
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Previously we have seen the image resizer takes in the whole data DMA makes the data transfer rate much faster, but there were several instances where CPU performed better and faster specifically in a wider range of image dimension color and size.

We intend to implement the following:
1. make faster multichannel operations at a hardware level integrated with similar high level software constructs
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    *1.a Highl Level Code structure to enable parallel operation and optimization*
    
    *1.b Maintain same level of parallelism (multiple data streams and logical processing constructs) in H/W level*

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2. make the FPGA capable to process images in as wide range as our CPU supports
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    *2.a CPU has large storage FPGA doesnot, we can make high level py code drive large data into DMA acceptable maximum chunks*

    *2.b Increase number of data channels into and out of FPGA for faster processing (higher utilization).*
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This is how a typical openCV resizer works:
<Data Transfer Image>

We will notice this further if we study the resizer code that in the 2d image is fed to our DMA and internally the whole image is read row by row , col by col. Image array size is static becuase we are have finite space in FPGA.

This may be made more efficient and robust (accomodating any image width) if by implementing the following changes:
1. Multichannel image operation where we use parallel threads for processing. Each of this processing an logic entity (utilizing multiple CLBs) is expected to be faster.
2. By chunking and sending data in packets fromour high level code we can also ensure that our FPGA can process an image much larger than it's own memory or DMA allocation space.

We use two streams of data in each process with it's own processing unit in our IP , which can be schematically represented in:
<image for our Implementation>
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In the background extraction technique we use a modified form of the watershed algorithm to suit different layers of the image with a similar range and intensity of pixels, so we have a customizable layer to extract.
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<Image modified watershed>
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# Tasks
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The Tasks and maximum estimated time:

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1. Problem statement and brainstorming for project selection : *24 hrs*
2. Design a basic model and build overlay : *4 hrs*
3. Python code adjustment and integration : *3 hrs*
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4. Plan next stage of overlay design : *2 hrs*
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# Resources used and Future project topics
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#### Resources used
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1. Image segmentation : https://theailearner.com/2020/11/29/image-segmentation-with-watershed-algorithm/
2. Operation with stream: https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_stream_library.html#ivv1539734234667__ad398476
3. Stream Interface : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/managing_interface_synthesis.html#ariaid-title32
3. Specialized Constructs : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/special_graph_constructs.html?hl=template
4. Vitis Examples : https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/cpp_kernels/README.md
5. Running Accelerator : https://pynq.readthedocs.io/en/v2.6.1/pynq_alveo.html#running-accelerators
6. Pragma Interfaces : https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/jit1504034365862.html
7. AXI4 : https://ch.mathworks.com/help/hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html
8. Interface of Streaming : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/managing_interface_synthesis.html#ariaid-title34
9. Database in FPGA : https://dspace.mit.edu/bitstream/handle/1721.1/91829/894228451-MIT.pdf, https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/accelerating-databases-with-fpgas.pdf, https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_process.html#djn1584047476918
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10. Muxed Stream : https://liu.diva-portal.org/smash/get/diva2:1057270/FULLTEXT01.pdf
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11. RAW,WAR,WAW.. : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_optimization_techniques.html#wen1539734225565__aa1299615
12: Loop Pipelining Roll Unroll : https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitis_hls_optimization_techniques.html#kcq1539734224846
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#### Future scope
The image processing can serve a stepping stone for controlling multi-agent systems. Where each streaming interface can be used for instruction input and output for each agent. Instead of using RTOS in each bot we can have multiple datastreams from each bots being processed in an IP designed to emulate a FSM for each agent and decide their action. This can lead to higher robustness and fault tolerance and lower costs. 

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# Errors Logs and Issues encountered
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The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
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Please check your design and connect them as needed: 
/color_filter/ap_start
When ap_Ctrl = None not specified in design
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Cant find custom IP in Vivado : add IP zip path, open IP Integrator view, from IP configure window manually add the IP
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Cant connect hls::stream<> type object in IP : Note: The hls::stream class should always be passed between functions as a C++ reference argument. For example, &my_stream.
IMPORTANT: The hls::stream class is only used in C++ designs. Array of streams is not supported.
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Non-Blocking write not-allowed in Non-FIFO Interfaces like axis instead try using FIFO m_axi
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DMA size must be lesser than 16383 so we cant feed very large datasets directly to a single DMA.
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WARNING: [HLS 200-786] Detected dataflow-on-top in function  'color_filter' (../project_3/color_filter.cpp:45)  with default interface mode 'ap_ctrl_hs'. Overlapped execution of successive kernel calls will not happen unless interface mode 'ap_ctrl_chain' is used (or 'ap_ctrl_none' for a purely data-driven design).
Resolution: For help on HLS 200-786 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-786.html