Commit f3ac6b9e authored by Rashed Al-Lahaseh's avatar Rashed Al-Lahaseh
Browse files

Merge branch 'development' into 'main'

First Release

See merge request !1
parents c7a5b565 d4f579a7
<mxfile host="www.diagrameditor.com" modified="2021-07-27T15:53:35.020Z" agent="Mozilla/5.0 (Macintosh; Intel Mac OS X 10_15_7) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/91.0.4472.114 Safari/537.36" etag="kb7shDgRjwPkXnXFRq3Q" version="12.1.3" pages="1"><diagram id="Pmxw0NCT1NgihB7Yrq5m" name="Page-1">7V1Zc5s6FP41fkwGEGJ5zNrcuU3H00xvlzfFKDa9GGUAO3Z//RWLzCKzOCyC63Q6U5DFJn3nnE+fjtQZuFnvPnnodfVILOzMFMnazcDtTFFkVVboP2HJPi6BuhYXLD3bSiqlBU/2H5wUSknpxrawn6sYEOIE9mu+cEFcFy+CXBnyPPKWr/ZCnPxTX9EScwVPC+Twpd9tK1jFpQaU0vIHbC9X7MmylPyyRqxyUuCvkEXeMkXgbgZuPEKC+Gi9u8FO2HisXeLr7kt+PbyYh92gyQV/z7Xf8/sf24fl9vnX+utfpvfJuUjuskXOJvng5GWDPWsB7FpXYUPSs4WDfN9ezMD1Klg7tECmh/Tx3v4HPZEuITv9GZ6yk9td7myfnMUPwhbX/ukHsQ5H3hIHFV+hHpqT4hCTNabPode9pR3G+muV6StW5mEHBfY2/xoowc3ycLvDE+bEpi+oSAzjrIP3+duyO/hk4y1wclG2f2ruI4PCjeJm4G5EDzJfnRZF3X8CFAAHha/YxwGHhwDvgjwCkguxR3+q7ku+j9gFUv7j2bdnulA90oWKVN5bufY5tTFUrjG+EHp+tQhs4tKDpwAFmGsaj2xcC1sJwN9WdoCfXtEi/PWNusfOW03LN5rJN9oBVNlW0/pqNdiBN9nZQcaZ0LOfmV9SVxKeME/SvweKbbgeL7WeShPpqQpw4aznvZ7qEKwH8lQ6jyrah0/JKfGCFVkSFzl3ael13jTTOp8JeU0A9hsHwT5hIGgTkOPAlDOwTEFaA0w5B8sUpf0DU2sXQk9DHLVstM9UeA0R4JcD8uDTGZCgVAm8Yn05T3noQfwGnaLN5JyaxOGPj4ke9u0/6DmqEHZp0hS0NryewVtaghx76YZukPYp9mhBGApsyjyvkh/WtmVF2HXQM3au0eLfZYTiG+IQL3oueIn+VAWThBcnb5K+fBZL5UZWGnmkS1nXjVxnMC75XifFqpCXF0Y7OvYbhki/MbGA1tRvyCUMpWNSDfRhQwyLaBmrlzn0/A+t3qi0+gvpUoJ5o1fGbvQa15GPZGu7S1r2BSPvOfy8Ofb8kNYX6fyKrJ83/iBU3iihVBlmaBxhhkZfVF7WpuIsO3R6clPBIVa1Wni9dn3DqzbffOpMFOkWB9TsaQ+MdIQKNNFDVBkKwbX4gC6bTbHdyVCgNqJrUrPRZ1dxQOH1rbOI6DHgq0K6AgAYexQ/MuYaaTgag6krTU3dFBrGFM4i7yITooQM+f4b8Wgc05zQIJ9pobYMj775MXebb/wV/ed6EwTE9SvinCwizqm66DinqFMxmC6B31SGVUqcYscxzhhYGJX5aYs7NwoZivSI1yTB1YgMRZeEGwrvhYTGmonpy81pZdshUycKM2OdTRVmmK/fj8LM2jADwX8oq7SiAVwmFo5HnoBHxnGDyhOK0DmgifFBBTYNiyXTk8PwQYWfPr7aIpuOmmzHDvZj1TQM8SHM+Ahhbcyj6VxHN6yxbQgztdNCmAEGCGGK+eGPuwcckLoAHIcQWIjmarNRyqnA5RLaJLUauaDtBTXVS767V8MAvFZ/FrKjUiItpbKjIcFu5xKTW5tHbzqARMnPNH5H/iqWqx7Rgh6FdP5qGzIa5wiNEUfnTUUwnVcnM9s4gvDBcmPrwwdoGT5a9Sl7zYw9zNF+jSNbHQeTh4X4ITyBFvAC3geTP8EygFhipRWGhk1T+E9lVloxW6S49KOm/iB5k+DDp/eB3LZj0HZx+kzZLCgRxlI2q04tLw7w+RBzRK8QSUthMb/bEMxLwWRk5i59UVO5GJRki7aVJ0BhmF5cUdf3Qjheh557ZIF9f7TEFbC0XHHMVagA+C6eKjDaGw0tTFW6sLC29FKFA9BFlR8unsU6G1AtlEmXkqzp+ajYjlowziLn+1jN36A/4qGKzUw6wVMIsXihmo3Kh76z4PdqSc5zaoQmyx/u1QgHE6sBP2WccJxYr74lrliFujgUUEUviNGAULc1LTmDAbnW3cG2Qlw7d6dwVvAQbhAzFpqvFbcWEb58Rp3MgHgMVtBU1FPb5uEfjy6HLHSW/FiERc8DaZWXmO5t1/ZX0QK1XLwZh70dgsxo7A1+RJ0T7K1pLjJsu2i9nQ/l030p/L3QcOPlLPQgTtu3KiximHT9okVowi1Ca6ITjF16EjdFyrTUd0tP6ZDIeN+ywVPVKN0sQNCsnuws1odmhXo16E4E/FB67L58AjhtPSHaiUSq1+xcZCjt6oNkUqJXCVbjh0Nnof5o1TEwXCKtsbTC8U7oQj4whvmHYxBztOIqLMiziEHFHDiZ1bEjoNWw6a4osIQyDEOr2Wtm8P8Z0R6LXuErIWt+MTmXn+vzdW4QtYx4+dFMuY7+joyT68IXm0Mxm6q8Y0pnDMymqTYqZEtGUNxTVq5ZglFMeRwitRDyqfZnMVcMa/dyMXSj210ZWTcfnf0agNQI3bNxYmkljT0LLNncc6BAzetfZzHMgLWbKxYSPS5absu0y9+mcNcBjJcfT95vostSUiVwVKIW8gyNIzxq2FGJXtZe45geKU5Hmj2KwfQ0/a8xYkCm/8EIuPsP</diagram></mxfile>
\ No newline at end of file
This diff is collapsed.
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 12:34:55 July 24, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "12:34:55 July 24, 2021"
# Revisions
PROJECT_REVISION = "Automated_Laundry_System"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 12:34:55 July 24, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Automated_Laundry_System_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY e_my_automated_laundry_system
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:34:55 JULY 24, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name BDF_FILE ../block_diagram_chart.bdf
set_global_assignment -name SDC_FILE Automated_Laundry_System.sdc
set_global_assignment -name VHDL_FILE e_my_automated_laundry_system.vhd
set_global_assignment -name VHDL_FILE e_7seg_display.vhd
set_global_assignment -name VHDL_FILE e_7seg_bcd_decoder.vhd
set_global_assignment -name VHDL_FILE e_laundry_fsm.vhd
set_global_assignment -name VHDL_FILE e_payment_fsm.vhd
set_global_assignment -name VHDL_FILE e_memory.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
## Generated SDC file "Automated_Laundry_System.sdc"
## Copyright (C) 2018 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
## DATE "Tue Jul 27 16:17:47 2021"
##
## DEVICE "5CSEMA5F31C6"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {CLOCK_50} -period 4.000 -waveform { 0.000 2.000 } [get_ports { CLOCK_50 }]
create_clock -name {e_payment_fsm:i_e_payment_fsm|sl_coin_state.two_euro_690} -period 4.000 -waveform { 0.000 2.000 } [get_registers { e_payment_fsm:i_e_payment_fsm|sl_coin_state.two_euro_690 }]
create_clock -name {reset} -period 4.000 -waveform { 0.000 2.000 } [get_ports { reset }]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {reset}] -rise_to [get_clocks {CLOCK_50}] 0.160
set_clock_uncertainty -rise_from [get_clocks {reset}] -fall_to [get_clocks {CLOCK_50}] 0.160
set_clock_uncertainty -fall_from [get_clocks {reset}] -rise_to [get_clocks {CLOCK_50}] 0.160
set_clock_uncertainty -fall_from [get_clocks {reset}] -fall_to [get_clocks {CLOCK_50}] 0.160
set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] -hold 0.060
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************
Info: Start Nativelink Simulation process
Info: NativeLink has detected VHDL design -- VHDL simulation models will be used
========= EDA Simulation Settings =====================
Sim Mode : RTL
Family : cyclonev
Quartus root : c:/intelfpga_lite/18.1/quartus/bin64/
Quartus sim root : c:/intelfpga_lite/18.1/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : vhdl
Version : 93
Simulation Mode : GUI
Sim Output File :
Sim SDF file :
Sim dir : simulation\modelsim
=======================================================
Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/intelfpga_lite/18.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File Automated_Laundry_System_run_msim_rtl_vhdl.do already exists - backing up current file as Automated_Laundry_System_run_msim_rtl_vhdl.do.bak1
Info: Spawning ModelSim-Altera Simulation software
Info: NativeLink simulation flow was successful
io_4iomodule_c5_index: 55gpio_index: 2
io_4iomodule_c5_index: 54gpio_index: 465
io_4iomodule_c5_index: 33gpio_index: 6
io_4iomodule_c5_index: 51gpio_index: 461
io_4iomodule_c5_index: 27gpio_index: 10
io_4iomodule_c5_index: 57gpio_index: 457
io_4iomodule_c5_index: 34gpio_index: 14
io_4iomodule_c5_index: 28gpio_index: 453
io_4iomodule_c5_index: 26gpio_index: 19
io_4iomodule_c5_index: 47gpio_index: 449
io_4iomodule_c5_index: 29gpio_index: 22
io_4iomodule_c5_index: 3gpio_index: 445
io_4iomodule_c5_index: 16gpio_index: 27
io_4iomodule_c5_index: 6gpio_index: 441
io_4iomodule_c5_index: 50gpio_index: 30
io_4iomodule_c5_index: 35gpio_index: 437
io_4iomodule_c5_index: 7gpio_index: 35
io_4iomodule_c5_index: 53gpio_index: 433
io_4iomodule_c5_index: 12gpio_index: 38
io_4iomodule_c5_index: 1gpio_index: 429
io_4iomodule_c5_index: 22gpio_index: 43
io_4iomodule_c5_index: 8gpio_index: 425
io_4iomodule_c5_index: 20gpio_index: 46
io_4iomodule_c5_index: 30gpio_index: 421
io_4iomodule_c5_index: 2gpio_index: 51
io_4iomodule_c5_index: 31gpio_index: 417
io_4iomodule_c5_index: 39gpio_index: 54
io_4iomodule_c5_index: 18gpio_index: 413
io_4iomodule_c5_index: 10gpio_index: 59
io_4iomodule_c5_index: 42gpio_index: 409
io_4iomodule_c5_index: 5gpio_index: 62
io_4iomodule_c5_index: 24gpio_index: 405
io_4iomodule_c5_index: 37gpio_index: 67
io_4iomodule_c5_index: 13gpio_index: 401
io_4iomodule_c5_index: 0gpio_index: 70
io_4iomodule_c5_index: 44gpio_index: 397
io_4iomodule_c5_index: 38gpio_index: 75
io_4iomodule_c5_index: 52gpio_index: 393
io_4iomodule_c5_index: 32gpio_index: 78
io_4iomodule_c5_index: 56gpio_index: 389
io_4iomodule_a_index: 13gpio_index: 385
io_4iomodule_c5_index: 4gpio_index: 83
io_4iomodule_c5_index: 23gpio_index: 86
io_4iomodule_a_index: 15gpio_index: 381
io_4iomodule_a_index: 8gpio_index: 377
io_4iomodule_c5_index: 46gpio_index: 91
io_4iomodule_a_index: 5gpio_index: 373
io_4iomodule_a_index: 11gpio_index: 369
io_4iomodule_c5_index: 41gpio_index: 94
io_4iomodule_a_index: 3gpio_index: 365
io_4iomodule_c5_index: 25gpio_index: 99
io_4iomodule_a_index: 7gpio_index: 361
io_4iomodule_c5_index: 9gpio_index: 102
io_4iomodule_a_index: 0gpio_index: 357
io_4iomodule_c5_index: 14gpio_index: 107
io_4iomodule_a_index: 12gpio_index: 353
io_4iomodule_c5_index: 45gpio_index: 110
io_4iomodule_c5_index: 17gpio_index: 115
io_4iomodule_a_index: 4gpio_index: 349
io_4iomodule_c5_index: 36gpio_index: 118
io_4iomodule_a_index: 10gpio_index: 345
io_4iomodule_a_index: 16gpio_index: 341
io_4iomodule_c5_index: 15gpio_index: 123
io_4iomodule_a_index: 14gpio_index: 337
io_4iomodule_c5_index: 43gpio_index: 126
io_4iomodule_c5_index: 19gpio_index: 131
io_4iomodule_a_index: 1gpio_index: 333
io_4iomodule_c5_index: 59gpio_index: 134
io_4iomodule_a_index: 2gpio_index: 329
io_4iomodule_a_index: 9gpio_index: 325
io_4iomodule_c5_index: 48gpio_index: 139
io_4iomodule_a_index: 6gpio_index: 321
io_4iomodule_a_index: 17gpio_index: 317
io_4iomodule_c5_index: 40gpio_index: 142
io_4iomodule_c5_index: 11gpio_index: 147
io_4iomodule_c5_index: 58gpio_index: 150
io_4iomodule_c5_index: 21gpio_index: 155
io_4iomodule_c5_index: 49gpio_index: 158
io_4iomodule_h_c5_index: 0gpio_index: 161
io_4iomodule_h_c5_index: 6gpio_index: 165
io_4iomodule_h_c5_index: 10gpio_index: 169
io_4iomodule_h_c5_index: 3gpio_index: 173
io_4iomodule_h_c5_index: 8gpio_index: 176
io_4iomodule_h_c5_index: 11gpio_index: 180
io_4iomodule_h_c5_index: 7gpio_index: 184
io_4iomodule_h_c5_index: 5gpio_index: 188
io_4iomodule_h_c5_index: 1gpio_index: 192
io_4iomodule_h_c5_index: 2gpio_index: 196
io_4iomodule_h_c5_index: 9gpio_index: 200
io_4iomodule_h_c5_index: 4gpio_index: 204
io_4iomodule_h_index: 15gpio_index: 208
io_4iomodule_h_index: 1gpio_index: 212
io_4iomodule_h_index: 3gpio_index: 216
io_4iomodule_h_index: 2gpio_index: 220
io_4iomodule_h_index: 11gpio_index: 224
io_4iomodule_vref_h_index: 1gpio_index: 228
io_4iomodule_h_index: 20gpio_index: 231
io_4iomodule_h_index: 8gpio_index: 235
io_4iomodule_h_index: 6gpio_index: 239
io_4iomodule_h_index: 10gpio_index: 243
io_4iomodule_h_index: 23gpio_index: 247
io_4iomodule_h_index: 7gpio_index: 251
io_4iomodule_h_index: 22gpio_index: 255
io_4iomodule_h_index: 5gpio_index: 259
io_4iomodule_h_index: 24gpio_index: 263
io_4iomodule_h_index: 0gpio_index: 267
io_4iomodule_h_index: 13gpio_index: 271
io_4iomodule_h_index: 21gpio_index: 275
io_4iomodule_h_index: 16gpio_index: 279
io_4iomodule_vref_h_index: 0gpio_index: 283
io_4iomodule_h_index: 12gpio_index: 286
io_4iomodule_h_index: 4gpio_index: 290
io_4iomodule_h_index: 19gpio_index: 294
io_4iomodule_h_index: 18gpio_index: 298
io_4iomodule_h_index: 17gpio_index: 302
io_4iomodule_h_index: 25gpio_index: 306
io_4iomodule_h_index: 14gpio_index: 310
io_4iomodule_h_index: 9gpio_index: 314
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment