Commit 040ea656 authored by Rashed Al-Lahaseh's avatar Rashed Al-Lahaseh
Browse files

Compilation and simulation files

parent 80f433ef
Assembler report for Automated_Laundry_System
Mon Jul 26 21:03:21 2021
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: C:/Project/output_files/Automated_Laundry_System.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Jul 26 21:03:21 2021 ;
; Revision Name ; Automated_Laundry_System ;
; Top-level Entity Name ; e_automated_laundry_system ;
; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+------------------------------------------------------+
; Assembler Generated Files ;
+------------------------------------------------------+
; File Name ;
+------------------------------------------------------+
; C:/Project/output_files/Automated_Laundry_System.sof ;
+------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Assembler Device Options: C:/Project/output_files/Automated_Laundry_System.sof ;
+----------------+---------------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------------+
; JTAG usercode ; 0x00B2876E ;
; Checksum ; 0x00B2876E ;
+----------------+---------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Info: Processing started: Mon Jul 26 21:03:08 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Automated_Laundry_System -c Automated_Laundry_System
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4824 megabytes
Info: Processing ended: Mon Jul 26 21:03:21 2021
Info: Elapsed time: 00:00:13
Info: Total CPU time (on all processors): 00:00:09
EDA Netlist Writer report for Automated_Laundry_System
Mon Jul 26 21:03:34 2021
Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Mon Jul 26 21:03:34 2021 ;
; Revision Name ; Automated_Laundry_System ;
; Top-level Entity Name ; e_automated_laundry_system ;
; Family ; Cyclone V ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Tool Name ; ModelSim-Altera (VHDL) ;
; Generate functional simulation netlist ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+------------------------+
+-------------------------------------------------------------+
; Simulation Generated Files ;
+-------------------------------------------------------------+
; Generated Files ;
+-------------------------------------------------------------+
; C:/Project/simulation/modelsim/Automated_Laundry_System.vho ;
+-------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Info: Processing started: Mon Jul 26 21:03:32 2021
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Automated_Laundry_System -c Automated_Laundry_System
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
Info (204019): Generated file Automated_Laundry_System.vho in folder "C:/Project/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 4741 megabytes
Info: Processing ended: Mon Jul 26 21:03:34 2021
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
This diff is collapsed.
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
Fitter Status : Successful - Mon Jul 26 21:03:06 2021
Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Revision Name : Automated_Laundry_System
Top-level Entity Name : e_automated_laundry_system
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Final
Logic utilization (in ALMs) : 83 / 32,070 ( < 1 % )
Total registers : 15
Total pins : 67 / 457 ( 15 % )
Total virtual pins : 0
Total block memory bits : 0 / 4,065,280 ( 0 % )
Total RAM Blocks : 0 / 397 ( 0 % )
Total DSP Blocks : 0 / 87 ( 0 % )
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 4 ( 0 % )
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