Commit b76b4bee authored by Pascal Fitzner's avatar Pascal Fitzner
Browse files

first_final

parent 2a8ede57
image: python
variables:
SSH_PRIVATE_KEY: $SSH_PRIVATE_KEY
SSH_KNOWN_HOSTS: $SSH_KNOWN_HOSTS
build-webpages:
stage: build
script:
- pip install -U sphinx-book-theme myst-parser
- make html
artifacts:
paths:
- _build/html
deploy-webpages:
stage: deploy
# from https://docs.gitlab.com/ee/ci/ssh_keys/
before_script:
- if [[ ! -v SSH_PRIVATE_KEY ]]; then echo SSH_PRIVATE_KEY not set.; exit 1; fi
- if [[ ! -v SSH_KNOWN_HOSTS ]]; then echo SSH_KNOWN_HOSTS not set.; exit 1; fi
- eval $(ssh-agent -s)
- echo "$SSH_PRIVATE_KEY" | tr -d '\r' | ssh-add -
- mkdir -p ~/.ssh
- chmod 700 ~/.ssh
- echo "$SSH_KNOWN_HOSTS" >> ~/.ssh/known_hosts
- chmod 644 ~/.ssh/known_hosts
script:
- ssh $GITLAB_USER_LOGIN@joan.th-deg.de -- rm -rf public_html/$CI_PROJECT_NAME
- scp -r _build/html $GITLAB_USER_LOGIN@joan.th-deg.de:public_html/$CI_PROJECT_NAME
except:
- merge_requests
`timescale 1ns / 1ps
module sin_pwm_tb;
reg clk_div_wave;
reg rst;
reg [15:0] sin_in;
reg sw_state;
wire pwm_out;
sin_to_pwm cut (.clk_div_wave(clk_div_wave), .rst(rst), .sin_in(sin_in), .sw_state(sw_state), .pwm_out(pwm_out));
parameter SIZE = 1024;
reg [15:0] rom_memory [SIZE-1:0];
integer i;
always #5 clk_div_wave = ~clk_div_wave;
initial
begin
clk_div_wave = 0;
sw_state = 1;
rst = 1;
$readmemh("sine.mem", rom_memory); //File with the signal
sin_in = 16'h8000;
i = 0;
#500;
rst = 0;
#20000 $finish;
end
always@(posedge clk_div_wave)
begin
if(rst) i = 0;
sin_in = rom_memory[i];
i = i+ 1;
if(i == SIZE)
i = 0;
end
endmodule
......@@ -52,23 +52,22 @@
proc checkRequiredFiles { origin_dir} {
set status true
set files [list \
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/clk_div.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/clk_div_wrapper.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/bcd_cnt.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/bcd_cnt_wrapper.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/led_cnt.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/led_cnt_wrapper.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/sw_cmp.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/sw_cmp_wrapper.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/clk_div_wave.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/clk_div_wave_wrapper.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/sin_to_pwm_.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/sin_to_pwm_wrapper.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/pwm_synt.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/synt_sin_lut_wrapper.v"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/sources_1/new/sine.mem"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/constrs_1/new/constrains.xdc"]"\
"[file normalize "$origin_dir/src-fpga-beat-machine.srcs/utils_1/imports/synth_1/design_beat_machine_wrapper.dcp"]"\
"[file normalize "clk_div.v"]"\
"[file normalize "clk_div_wrapper.v"]"\
"[file normalize "bcd_cnt.v"]"\
"[file normalize "bcd_cnt_wrapper.v"]"\
"[file normalize "led_cnt.v"]"\
"[file normalize "led_cnt_wrapper.v"]"\
"[file normalize "sw_cmp.v"]"\
"[file normalize "sw_cmp_wrapper.v"]"\
"[file normalize "clk_div_wave.v"]"\
"[file normalize "clk_div_wave_wrapper.v"]"\
"[file normalize "sin_to_pwm_.v"]"\
"[file normalize "sin_to_pwm_wrapper.v"]"\
"[file normalize "pwm_synt.v"]"\
"[file normalize "synt_sin_lut_wrapper.v"]"\
"[file normalize "sine.mem"]"\
"[file normalize "constrains.xdc"]"\
]
foreach ifile $files {
if { ![file isfile $ifile] } {
......@@ -78,8 +77,8 @@ proc checkRequiredFiles { origin_dir} {
}
set files [list \
"[file normalize "$origin_dir/../../project_synt/project_synt.srcs/sim_1/new/sin_pwm_tb.v"]"\
"[file normalize "$origin_dir/../../project_synt/project_synt.srcs/sim_1/new/synt_sin_lut_tb.v"]"\
"[file normalize "sin_pwm_tb.v"]"\
"[file normalize "synt_sin_lut_tb.v"]"\
]
foreach ifile $files {
if { ![file isfile $ifile] } {
......@@ -197,21 +196,21 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
set obj [get_filesets sources_1]
# Import local files from the original project
set files [list \
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/clk_div.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/clk_div_wrapper.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/bcd_cnt.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/bcd_cnt_wrapper.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/led_cnt.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/led_cnt_wrapper.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/sw_cmp.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/sw_cmp_wrapper.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/clk_div_wave.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/clk_div_wave_wrapper.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/sin_to_pwm_.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/sin_to_pwm_wrapper.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/pwm_synt.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/synt_sin_lut_wrapper.v" ]\
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/sources_1/new/sine.mem" ]\
[file normalize "clk_div.v" ]\
[file normalize "clk_div_wrapper.v" ]\
[file normalize "bcd_cnt.v" ]\
[file normalize "bcd_cnt_wrapper.v" ]\
[file normalize "led_cnt.v" ]\
[file normalize "led_cnt_wrapper.v" ]\
[file normalize "sw_cmp.v" ]\
[file normalize "sw_cmp_wrapper.v" ]\
[file normalize "clk_div_wave.v" ]\
[file normalize "clk_div_wave_wrapper.v" ]\
[file normalize "sin_to_pwm_.v" ]\
[file normalize "sin_to_pwm_wrapper.v" ]\
[file normalize "pwm_synt.v" ]\
[file normalize "synt_sin_lut_wrapper.v" ]\
[file normalize "sine.mem" ]\
]
set imported_files [import_files -fileset sources_1 $files]
......@@ -219,81 +218,82 @@ set imported_files [import_files -fileset sources_1 $files]
# None
# Set 'sources_1' fileset file properties for local files
set file "new/clk_div.v"
set file "clk_div.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/clk_div_wrapper.v"
set file "clk_div_wrapper.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/bcd_cnt.v"
set file "bcd_cnt.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/bcd_cnt_wrapper.v"
set file "bcd_cnt_wrapper.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/led_cnt.v"
set file "led_cnt.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/led_cnt_wrapper.v"
set file "led_cnt_wrapper.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/sw_cmp.v"
set file "sw_cmp.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/sw_cmp_wrapper.v"
set file "sw_cmp_wrapper.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/clk_div_wave.v"
set file "clk_div_wave.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/clk_div_wave_wrapper.v"
set file "clk_div_wave_wrapper.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/sin_to_pwm_.v"
set file "sin_to_pwm_.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/sin_to_pwm_wrapper.v"
set file "sin_to_pwm_wrapper.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/pwm_synt.v"
set file "pwm_synt.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/synt_sin_lut_wrapper.v"
set file "synt_sin_lut_wrapper.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
set_property -name "used_in_simulation" -value "0" -objects $file_obj
set file "new/sine.mem"
set file "sine.mem"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Memory File" -objects $file_obj
......@@ -311,9 +311,9 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/src-fpga-beat-machine.srcs/constrs_1/new/constrains.xdc"]"
set file "[file normalize "constrains.xdc"]"
set file_imported [import_files -fileset constrs_1 [list $file]]
set file "new/constrains.xdc"
set file "constrains.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj
......@@ -329,8 +329,8 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
set files [list \
[file normalize "${origin_dir}/../../project_synt/project_synt.srcs/sim_1/new/sin_pwm_tb.v"] \
[file normalize "${origin_dir}/../../project_synt/project_synt.srcs/sim_1/new/synt_sin_lut_tb.v"] \
[file normalize "sin_pwm_tb.v"] \
[file normalize "synt_sin_lut_tb.v"] \
]
add_files -norecurse -fileset $obj $files
......@@ -346,22 +346,6 @@ set_property -name "top" -value "sin_pwm_tb" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
# Set 'utils_1' fileset object
set obj [get_filesets utils_1]
# Import local files from the original project
set files [list \
[file normalize "${origin_dir}/src-fpga-beat-machine.srcs/utils_1/imports/synth_1/design_beat_machine_wrapper.dcp" ]\
]
set imported_files [import_files -fileset utils_1 $files]
# Set 'utils_1' fileset file properties for remote files
# None
# Set 'utils_1' fileset file properties for local files
set file "synth_1/design_beat_machine_wrapper.dcp"
set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
set_property -name "netlist_only" -value "0" -objects $file_obj
# Set 'utils_1' fileset properties
set obj [get_filesets utils_1]
......@@ -659,10 +643,10 @@ if { $obj != "" } {
}
set obj [get_runs synth_1]
set_property -name "part" -value "xc7s50csga324-1" -objects $obj
set_property -name "incremental_checkpoint" -value "$proj_dir/src-fpga-beat-machine.srcs/utils_1/imports/synth_1/design_beat_machine_wrapper.dcp" -objects $obj
set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
# set the current synth run
current_run -synthesis [get_runs synth_1]
......
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