Commit 9983cc98 authored by Majd Hafiri's avatar Majd Hafiri
Browse files

added synth and simulation script

parent 48c699ed
# Change the Syn top module you wish to simulate, as well as the testbench name
SYN_TOP = pwm_generator ## (other modules -> one_Hz_clock, servo_control, seven_segment_display, slow_clock, slow_counter)
SIM_TOP = pwm_testbench ## (other testbenches -> one_hz_clk_testbench, servo_control_testbench, seven_segment_testbench, slow_clock_testbench, slow_counter_testbench)
SRCS = \
ROBOTIC_ARM/ROBOTIC_ARM.srcs/sources_1/new/$(SYN_TOP).sv \
ROBOTIC_ARM/ROBOTIC_ARM.srcs/sim_1/new/$(SIM_TOP).sv
# Tool options
SIMOPTS ?= --nolog # xsim simulation options
ELAB_DEBUG_ARG ?= typical
# Default goal
sim: sim-gui
sim-compile:
xvlog --sv \
$(SIMOPTS) \
$(SRCS)
sim-elaborate: sim-compile
xelab \
$(SIMOPTS) --debug $(ELAB_DEBUG_ARG) \
$(SIM_TOP)
# Generates executable code for simulation
signals.tcl:
echo 'add_wave *' > $@
echo run all >> $@
# Adds signals to the waveform window
sim-gui: signals.tcl sim-elaborate
xsim \
$(SIMOPTS) --gui \
--tclbatch signals.tcl\
$(SIM_TOP)
# Launches simulation in projectless mode
sim-clean:
$(RM) {xvlog,xelab}.pb
$(RM) {xvlog,xelab}.log
# the tools still generate a logfile if executed alone, e.g.: xvlog -h
$(RM) -r xsim.dir
$(RM) xsim.jou xsim_* # journal (.jou) files
$(RM) *.{wcfg,wdb}
sim-clean-all: clean
$(RM) signals.tcl
clean: sim-clean
clean-all: sim-clean-all
SYN_TOP = $(basename $(lastword $(wildcard *.v)))
SYN_TOP_FILE = $(SYN_TOP).sv
# If only TOP.v and TOP_tb.v exist, firstword returns TOP_tb.v, lastword TOP.v
DESIGN_FILES = \
$(SYN_TOP_FILE) \
$(DESIGN_CONSTRAINTS_FILE)
PART := xc7s50csga324-1
DESIGN_CONSTRAINTS_FILE ?= constraints.xdc
DESIGN_CONSTRAINTS_URL := \
https://www.realdigital.org/downloads/8d5c167add28c014173edcf51db78bb9.txt
# Configuration end ###########################################################
BITSTREAM := $(SYN_TOP)
# Default goal
.PHONY: syn
syn: program
.PHONY: program
program: program.tcl $(BITSTREAM)
vivado $(VIVADO_OPT) -source $<
.PHONY: $(SYN_TOP)
bitstream: robotic_arm
SYN_PROJ := syn-proj/syn.xpr
.PHONY: syn-proj
syn-proj: $(SYN_PROJ)
VIVADO_OPT := \
-tempDir /tmp \
-nojournal \
-applog \
-mode batch
$(SYN_PROJ): syn-proj.tcl
vivado $(VIVADO_OPT) -source $<
syn-proj.tcl:
@echo create_project -part $(PART) syn.xpr syn-proj > $@
@echo add_files $(SYN_TOP_FILE) >> $@
@echo set_property file_type SystemVerilog [get_files $(SYN_TOP_FILE)] >> $@
@echo add_files $(DESIGN_CONSTRAINTS_FILE) >> $@
@echo set_property top $(SYN_TOP) [current_fileset] >> $@
@echo exit >> $@
$(DESIGN_CONSTRAINTS_FILE):
curl $(DESIGN_CONSTRAINTS_URL) > $@
$(BITSTREAM): \
syn.tcl \
$(DESIGN_FILES) \
| $(SYN_PROJ)
vivado $(VIVADO_OPT) -source $<
# Run synthesis
## based on
## https://docs.xilinx.com/r/en-US/ug892-vivado-design-flows-overview/Using-Non-Project-Mode-Tcl-Commands
## TODO create a non-project flow
syn.tcl:
@echo open_project $(SYN_PROJ) > $@
@echo synth_design >> $@
@echo opt_design >> $@
@echo place_design >> $@
@echo phys_opt_design >> $@
@echo route_design >> $@
@echo report_timing_summary >> $@
@echo report_utilization >> $@
@echo report_power >> $@
@echo write_bitstream -force robotic_arm >> $@
program.tcl:
@echo open_hw_manager > $@
@echo connect_hw_server >> $@
@echo open_hw_target >> $@
@echo current_hw_device >> $@
@echo puts \"Selected device: [current_hw_device]\" >> $@
@echo set_property PROGRAM.FILE robotic_arm.bit [current_hw_device] >> $@
@echo program_hw_device >> $@
syn-clean:
# Does not clean .tcl files. They could have been modified by the user.
$(RM) vivado*.log
$(RM) -r syn-proj
$(RM) $(BITSTREAM)
clean: syn-clean
syn-clean-all: syn-clean
# Additionally removes files potentially user-modified files
$(RM) syn-proj.tcl syn.tcl program.tcl
$(RM) $(DESIGN_CONSTRAINTS_FILE)
clean-all: syn-clean-all
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment