Commit 1f49692b authored by Majd Hafiri's avatar Majd Hafiri
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Update README.md

parent b204f285
......@@ -25,4 +25,9 @@
Each module has a testbench, therefore it should be simulated individually. In Vivado, Go to `tools -> settings -> Simulation` and select the testbench you wish to simulate in the `simulation top module name`. Additionally, change the simulation `runtime` to a high number(eg. 100000000 ns) since some modules require that in order to see the changes of their outputs.
## Synthesize & simulate ( without GUI )
1. Activate vivado : `. /tools/Xilinx/Vivado/2021.2/settings64.sh` ( Select the right path )
2. Simulation : `make -f vsim.mk` ( other testbenches can be simulated by modifying the vsim file -> explanation in the file )
3. Synthesis : `make -f vsyn.mk` (Needs some more modifications)
- Credits: [https://mygit.th-deg.de/gaydos/realdigital-boolean-makefile/-/tree/main](https://mygit.th-deg.de/gaydos/realdigital-boolean-makefile/-/tree/main)
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