Add auto file selection

iverilog.mk

-TOP ?= comb_circ_using_delays_tb
-SRCADD ?= comb_circ_using_delays.v
+TOP ?= $(basename $(firstword $(wildcard *.v)))
+SRCADD ?= $(lastword $(wildcard *.v))
+# If only TOP.v and TOP_tb.v exist, firstword returns TOP_tb.v, lastword TOP.v
+IVERILOG_OPTS ?= -g2012
 
 default: signals.vcd
 
@@ -9,6 +11,7 @@ SRC = $(TOP).v $(SRCADD)
 # Creates the model for simulation
 $(SIM_MODEL): $(SRC)
 	iverilog \
+		$(IVERILOG_OPTS) \
 		-o $(TOP) \
 		$^