Commit 6c75310e authored by goekce's avatar goekce
Browse files

Add auto file selection

parent d74640e9
TOP ?= comb_circ_using_delays_tb
SRCADD ?= comb_circ_using_delays.v
TOP ?= $(basename $(firstword $(wildcard *.v)))
SRCADD ?= $(lastword $(wildcard *.v))
# If only TOP.v and TOP_tb.v exist, firstword returns TOP_tb.v, lastword TOP.v
default: signals.vcd
......@@ -9,6 +11,7 @@ SRC = $(TOP).v $(SRCADD)
# Creates the model for simulation
iverilog \
-o $(TOP) \
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