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# Minimal Example for Verilog Simulation using Icarus Verilog

[Icarus Verilog (iverilog)](http://iverilog.icarus.com/) is an open-source Verilog simulator which also supports delay statements like `#42` compared to [Verilator](https://verilator.org/guide).

If you do not need these statements, then you should use Verilator for which I also compiled a [minimal example][verilator-minimal-example].

## Getting Started

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The example features a glitch formation. The glitch can be seen on the output `X` towards the end. Follow instructions in the [Verilator minimal example][verilator-minimal-example], but install Iverilog instead of Verilator.
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[verilator-minimal-example]: https://mygit.th-deg.de/gaydos/verilator-minimal-example